收藏

文件名称:cpu

  • 所属分类：
  • 其它资源
  • 资源属性：
  • [ASM] [源码]
  • 上传时间：
  • 2008-10-13
  • 文件大小：
  • 1.59mb
  • 下载次数：
  • 0次
  • 提 供 者：
  • gexi*****
  • 相关连接：
  • 无
  • 下载说明：
  • 别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容均来自于网络，请自行研究使用

本人制作的8位CPU,有简单的加减,输入,输出操作,希望大家好用
(系统自动生成,下载前可以参看下载内容)

下载文件列表

压缩包 : 119128669cpu.rar 列表
80386.zip
IT51_src[1].tar.gz
openrisc1200\or1k\or1200\CVS\Root
openrisc1200\or1k\or1200\CVS\Repository
openrisc1200\or1k\or1200\CVS\Entries
openrisc1200\or1k\or1200\CVS
openrisc1200\or1k\or1200\bench\CVS\Root
openrisc1200\or1k\or1200\bench\CVS\Repository
openrisc1200\or1k\or1200\bench\CVS\Entries
openrisc1200\or1k\or1200\bench\CVS
openrisc1200\or1k\or1200\bench\README
openrisc1200\or1k\or1200\bench
openrisc1200\or1k\or1200\doc\CVS\Root
openrisc1200\or1k\or1200\doc\CVS\Repository
openrisc1200\or1k\or1200\doc\CVS\Entries
openrisc1200\or1k\or1200\doc\CVS
openrisc1200\or1k\or1200\doc\or1200_spec.doc
openrisc1200\or1k\or1200\doc\or1200_spec.pdf
openrisc1200\or1k\or1200\doc
openrisc1200\or1k\or1200\lib\CVS\Root
openrisc1200\or1k\or1200\lib\CVS\Repository
openrisc1200\or1k\or1200\lib\CVS\Entries
openrisc1200\or1k\or1200\lib\CVS
openrisc1200\or1k\or1200\lib\README
openrisc1200\or1k\or1200\lib
openrisc1200\or1k\or1200\lint\CVS\Root
openrisc1200\or1k\or1200\lint\CVS\Repository
openrisc1200\or1k\or1200\lint\CVS\Entries
openrisc1200\or1k\or1200\lint\CVS
openrisc1200\or1k\or1200\lint\bin\CVS\Root
openrisc1200\or1k\or1200\lint\bin\CVS\Repository
openrisc1200\or1k\or1200\lint\bin\CVS\Entries
openrisc1200\or1k\or1200\lint\bin\CVS
openrisc1200\or1k\or1200\lint\bin\README
openrisc1200\or1k\or1200\lint\bin\run_lint
openrisc1200\or1k\or1200\lint\bin
openrisc1200\or1k\or1200\lint\log\CVS\Root
openrisc1200\or1k\or1200\lint\log\CVS\Repository
openrisc1200\or1k\or1200\lint\log\CVS\Entries
openrisc1200\or1k\or1200\lint\log\CVS
openrisc1200\or1k\or1200\lint\log\README
openrisc1200\or1k\or1200\lint\log
openrisc1200\or1k\or1200\lint\run\CVS\Root
openrisc1200\or1k\or1200\lint\run\CVS\Repository
openrisc1200\or1k\or1200\lint\run\CVS\Entries
openrisc1200\or1k\or1200\lint\run\CVS
openrisc1200\or1k\or1200\lint\run\README
openrisc1200\or1k\or1200\lint\run
openrisc1200\or1k\or1200\lint
openrisc1200\or1k\or1200\rtl\CVS\Root
openrisc1200\or1k\or1200\rtl\CVS\Repository
openrisc1200\or1k\or1200\rtl\CVS\Entries
openrisc1200\or1k\or1200\rtl\CVS
openrisc1200\or1k\or1200\rtl\verilog\CVS\Root
openrisc1200\or1k\or1200\rtl\verilog\CVS\Repository
openrisc1200\or1k\or1200\rtl\verilog\CVS\Entries
openrisc1200\or1k\or1200\rtl\verilog\CVS
openrisc1200\or1k\or1200\rtl\verilog\or1200_alu.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_amultp2_32x32.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_cfgr.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_cpu.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_ctrl.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_dc_fsm.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_dc_ram.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_dc_tag.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_dc_top.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_defines.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_dmmu_tlb.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_dmmu_top.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_dpram_256x32.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_dpram_32x32.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_du.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_except.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_freeze.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_genpc.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_gmultp2_32x32.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_ic_fsm.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_ic_ram.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_ic_tag.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_ic_top.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_if.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_immu_tlb.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_immu_top.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_iwb_biu.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_lsu.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_mem2reg.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_mult_mac.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_operandmuxes.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_pic.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_pm.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_qmem_top.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_reg2mem.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_rf.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_rfram_generic.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_sb.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_sb_fifo.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_spram_1024x32.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_spram_1024x32_bw.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_spram_1024x8.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_spram_128x32.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_spram_2048x32.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_spram_2048x32_bw.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_spram_2048x8.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_spram_256x21.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_spram_32x24.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_spram_512x20.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_spram_64x14.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_spram_64x22.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_spram_64x24.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_sprs.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_top.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_tpram_32x32.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_tt.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_wb_biu.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_wbmux.v
openrisc1200\or1k\or1200\rtl\verilog\or1200_xcv_ram32x8d.v
openrisc1200\or1k\or1200\rtl\verilog\timescale.v
openrisc1200\or1k\or1200\rtl\verilog
openrisc1200\or1k\or1200\rtl
openrisc1200\or1k\or1200\sim\CVS\Root
openrisc1200\or1k\or1200\sim\CVS\Repository
openrisc1200\or1k\or1200\sim\CVS\Entries
openrisc1200\or1k\or1200\sim\CVS
openrisc1200\or1k\or1200\sim\README
openrisc1200\or1k\or1200\sim
openrisc1200\or1k\or1200\syn\CVS\Root
openrisc1200\or1k\or1200\syn\CVS\Repository
openrisc1200\or1k\or1200\syn\CVS\Entries
openrisc1200\or1k\or1200\syn\CVS
openrisc1200\or1k\or1200\syn\gate\CVS\Root
openrisc1200\or1k\or1200\syn\gate\CVS\Repository
openrisc1200\or1k\or1200\syn\gate\CVS\Entries
openrisc1200\or1k\or1200\syn\gate\CVS
openrisc1200\or1k\or1200\syn\gate
openrisc1200\or1k\or1200\syn\logs\CVS\Root
openrisc1200\or1k\or1200\syn\logs\CVS\Repository
openrisc1200\or1k\or1200\syn\logs\CVS\Entries
openrisc1200\or1k\or1200\syn\logs\CVS
openrisc1200\or1k\or1200\syn\logs
openrisc1200\or1k\or1200\syn\scr\CVS\Root
openrisc1200\or1k\or1200\syn\scr\CVS\Repository
openrisc1200\or1k\or1200\syn\scr\CVS\Entries
openrisc1200\or1k\or1200\syn\scr\CVS
openrisc1200\or1k\or1200\syn\scr
openrisc1200\or1k\or1200\syn\synopsys\CVS\Root
openrisc1200\or1k\or1200\syn\synopsys\CVS\Repository
openrisc1200\or1k\or1200\syn\synopsys\CVS\Entries
openrisc1200\or1k\or1200\syn\synopsys\CVS
openrisc1200\or1k\or1200\syn\synopsys\bin\CVS\Root
openrisc1200\or1k\or1200\syn\synopsys\bin\CVS\Repository
openrisc1200\or1k\or1200\syn\synopsys\bin\CVS\Entries
openrisc1200\or1k\or1200\syn\synopsys\bin\CVS
openrisc1200\or1k\or1200\syn\synopsys\bin\README
openrisc1200\or1k\or1200\syn\synopsys\bin\read_design.inc
openrisc1200\or1k\or1200\syn\synopsys\bin\run_syn
openrisc1200\or1k\or1200\syn\synopsys\bin\top.scr
openrisc1200\or1k\or1200\syn\synopsys\bin
openrisc1200\or1k\or1200\syn\synopsys\log\CVS\Root
openrisc1200\or1k\or1200\syn\synopsys\log\CVS\Repository
openrisc1200\or1k\or1200\syn\synopsys\log\CVS\Entries
openrisc1200\or1k\or1200\syn\synopsys\log\CVS
openrisc1200\or1k\or1200\syn\synopsys\log\README
openrisc1200\or1k\or1200\syn\synopsys\log
openrisc1200\or1k\or1200\syn\synopsys\out\CVS\Root
openrisc1200\or1k\or1200\syn\synopsys\out\CVS\Repository
openrisc1200\or1k\or1200\syn\synopsys\out\CVS\Entries
openrisc1200\or1k\or1200\syn\synopsys\out\CVS
openrisc1200\or1k\or1200\syn\synopsys\out\README
openrisc1200\or1k\or1200\syn\synopsys\out
openrisc1200\or1k\or1200\syn\synopsys\run\CVS\Root
openrisc1200\or1k\or1200\syn\synopsys\run\CVS\Repository
openrisc1200\or1k\or1200\syn\synopsys\run\CVS\Entries
openrisc1200\or1k\or1200\syn\synopsys\run\CVS
openrisc1200\or1k\or1200\syn\synopsys\run\README
openrisc1200\or1k\or1200\syn\synopsys\run
openrisc1200\or1k\or1200\syn\synopsys
openrisc1200\or1k\or1200\syn
openrisc1200\or1k\or1200
openrisc1200\or1k
openrisc1200
8051core-Verilog.zip
8088verilog.zip
8088vhdl.zip

相关说明

  • 本站资源为会员上传分享交流与学习,如有侵犯您的权益,请联系我们删除.
  • 本站是交换下载平台，提供交流渠道，下载内容来自于网络，除下载问题外，其它问题请自行百度。更多...
  • 请直接用浏览器下载本站内容，不要使用迅雷之类的下载软件，用WinRAR最新版进行解压.
  • 如果您发现内容无法下载，请稍后再次尝试；或者到消费记录里找到下载记录反馈给我们.
  • 下载后发现下载的内容跟说明不相乎，请到消费记录里找到下载记录反馈给我们，经确认后退回积分.
  • 如下载前有疑问，可以通过点击"提供者"的名字，查看对方的联系方式，联系对方咨询.
查看所有评论

相关评论

暂无评论内容．

发表评论

*主　　题：
*内　　容：
*验 证 码：

源码中国 www.ymcn.org