The Vedic mathematics is quite different from

conventional method of multiplication like adder and shifter.

This mathematics is mainly based on sixteen principles. The

multiplier (referred henceforth as Vedic multiplier)

architecture based on the URDHVA TIRYAKBHYAM

(Vertically and cross wise) sutra is presented. The existing

method is 16*16 bit multiplication in relatively less speed. The

proposed method is 32*32 bit multiplication in terms of

relatively high speed, low power, less area and less delay. This

will help in designing multiplier in VHDL, as its give effective

utilization of structural method of modelling. This also gives

chances for modular design where smaller block can be used to

design the bigger one.-The Vedic mathematics is quite different from

conventional method of multiplication like adder and shifter.

This mathematics is mainly based on sixteen principles. The

multiplier (referred henceforth as Vedic multiplier)

architecture based on the URDHVA TIRYAKBHYAM

(Vertically and cross wise) sutra is presented. The existing

method is 16*16 bit multiplication in relatively less speed. The

proposed method is 32*32 bit multiplication in terms of

relatively high speed, low power, less area and less delay. This

will help in designing multiplier in VHDL, as its give effective

utilization of structural method of modelling.　This also gives

chances for modular design where smaller block can be used to

design the bigger one.