文件名称:MEMCTRL
介绍说明－－下载内容均来自于网络，请自行研究使用
存储器控制器，采用verilog描述，FPGA实现-memory controler
(系统自动生成,下载前可以参看下载内容)
下载文件列表
MEMCTRL\cmp_state.ini
.......\db\add_sub_d5h.tdf
.......\..\add_sub_e5h.tdf
.......\..\add_sub_fch.tdf
.......\..\add_sub_jhh.tdf
.......\..\add_sub_n6h.tdf
.......\..\mc_top-sim.vwf
.......\..\mc_top.asm.qmsg
.......\..\mc_top.cmp.cdb
.......\..\mc_top.cmp.ddb
.......\..\mc_top.cmp.hdb
.......\..\mc_top.cmp.rdb
.......\..\mc_top.cmp.tdb
.......\..\mc_top.csf.qmsg
.......\..\mc_top.db_info
.......\..\mc_top.eda.qmsg
.......\..\mc_top.fit.qmsg
.......\..\mc_top.hif
.......\..\mc_top.icc
.......\..\mc_top.map.cdb
.......\..\mc_top.map.hdb
.......\..\mc_top.map.qmsg
.......\..\mc_top.mc_top.sld_design_entry.sci
.......\..\mc_top.pre_map.hdb
.......\..\mc_top.project.hdb
.......\..\mc_top.rtlv.hdb
.......\..\mc_top.rtlv_sg.cdb
.......\..\mc_top.rtlv_sg_swap.cdb
.......\..\mc_top.sgdiff.cdb
.......\..\mc_top.sgdiff.hdb
.......\..\mc_top.signalprobe.cdb
.......\..\mc_top.sim.hdb
.......\..\mc_top.sim.qmsg
.......\..\mc_top.sim.rdb
.......\..\mc_top.tan.qmsg
.......\..\mc_top_cmp.qrpt
.......\..\mc_top_hier_info
.......\..\mc_top_sim.qrpt
.......\..\mc_top_syn_hier_info
.......\mc_adr_sel.v
.......\mc_cs_rf.v
.......\mc_defines.v
.......\mc_defines.v.bak
.......\mc_dp.v
.......\mc_incn_r.v
.......\mc_mem_if.v
.......\mc_obct.v
.......\mc_obct_top.v
.......\mc_rd_fifo.v
.......\mc_refresh.v
.......\mc_rf.v
.......\mc_timing.v
.......\mc_top.asm.rpt
.......\mc_top.done
.......\mc_top.eda.rpt
.......\mc_top.fit.eqn
.......\mc_top.fit.rpt
.......\mc_top.flow.rpt
.......\mc_top.map.eqn
.......\mc_top.map.rpt
.......\mc_top.pin
.......\mc_top.pof
.......\mc_top.qpf
.......\mc_top.qsf
.......\mc_top.qws
.......\mc_top.sim.rpt
.......\mc_top.sof
.......\mc_top.tan.rpt
.......\mc_top.tan.summary
.......\mc_top.v
.......\mc_top.vwf
.......\mc_wb_if.v
.......\simulation\modelsim\mc_top.vo
.......\..........\........\mc_top_modelsim.xrf
.......\..........\........\mc_top_v.sdo
.......\verilog\160b3ver\adv_bb.v
.......\.......\........\CVS\Entries
.......\.......\........\...\Repository
.......\.......\........\...\Root
.......\.......\........\dp160b3b.v
.......\.......\........\DP160B3B_RU.V
.......\.......\........\dp160b3t.v
.......\.......\........\f160b3b.bkb
.......\.......\........\f160b3b.bke
.......\.......\........\f160b3b.bkt
.......\.......\........\f160b3t.bkb
.......\.......\........\f160b3t.bke
.......\.......\........\f160b3t.bkt
.......\.......\........\read.me
.......\.......\........\t160b3b.v
.......\.......\........\t160b3t.v
.......\.......\CVS\Entries
.......\.......\...\Repository
.......\.......\...\Root
.......\.......\sdram_models\16Mx16\CVS\Entries
.......\.......\............\......\...\Repository
.......\.......\............\......\...\Root
.......\.......\............\......\mt48lc16m16a2.v
.......\.......\............\....8\CVS\Entries
.......\.......\............\.....\...\Repository