文件名称:VGA
介绍说明－－下载内容均来自于网络，请自行研究使用
FPGA verilog写的关于vGA的显示程序，使用vivado编程环境-FPGA verilog written on the vGA display program, the use of vivado programming environment
(系统自动生成,下载前可以参看下载内容)
下载文件列表
VGA\file_vga\vga.v
...\........\vga.xdc
...\lab_vga\hs_err_pid4488.log
...\.......\lab_vga.cache\wt\java_command_handlers.wdf
...\.......\.............\..\synthesis.wdf
...\.......\.............\..\webtalk_pa.xml
...\.......\........runs\.jobs\vrs_config_1.xml
...\.......\............\.....\vrs_config_10.xml
...\.......\............\.....\vrs_config_11.xml
...\.......\............\.....\vrs_config_12.xml
...\.......\............\.....\vrs_config_13.xml
...\.......\............\.....\vrs_config_14.xml
...\.......\............\.....\vrs_config_15.xml
...\.......\............\.....\vrs_config_2.xml
...\.......\............\.....\vrs_config_3.xml
...\.......\............\.....\vrs_config_4.xml
...\.......\............\.....\vrs_config_5.xml
...\.......\............\.....\vrs_config_6.xml
...\.......\............\.....\vrs_config_7.xml
...\.......\............\.....\vrs_config_8.xml
...\.......\............\.....\vrs_config_9.xml
...\.......\............\clk_wiz_0_synth_1\.Vivado Synthesis.queue.rst
...\.......\............\.................\.vivado.begin.rst
...\.......\............\.................\.vivado.end.rst
...\.......\............\.................\.Xil\clk_wiz_0_propImpl.xdc
...\.......\............\.................\clk_wiz_0.dcp
...\.......\............\.................\clk_wiz_0.tcl
...\.......\............\.................\clk_wiz_0.vds
...\.......\............\.................\clk_wiz_0_utilization_synth.pb
...\.......\............\.................\clk_wiz_0_utilization_synth.rpt
...\.......\............\.................\dont_touch.xdc
...\.......\............\.................\gen_run.xml
...\.......\............\.................\htr.txt
...\.......\............\.................\ISEWrap.js
...\.......\............\.................\ISEWrap.sh
...\.......\............\.................\project.wdf
...\.......\............\.................\rundef.js
...\.......\............\.................\runme.bat
...\.......\............\.................\runme.log
...\.......\............\.................\runme.sh
...\.......\............\.................\vivado.jou
...\.......\............\.................\vivado.pb
...\.......\............\impl_1\.init_design.begin.rst
...\.......\............\......\.init_design.end.rst
...\.......\............\......\.opt_design.begin.rst
...\.......\............\......\.opt_design.end.rst
...\.......\............\......\.place_design.begin.rst
...\.......\............\......\.place_design.end.rst
...\.......\............\......\.route_design.begin.rst
...\.......\............\......\.route_design.end.rst
...\.......\............\......\.Vivado Implementation.queue.rst
...\.......\............\......\.vivado.begin.rst
...\.......\............\......\.vivado.end.rst
...\.......\............\......\.write_bitstream.begin.rst
...\.......\............\......\.write_bitstream.end.rst
...\.......\............\......\gen_run.xml
...\.......\............\......\htr.txt
...\.......\............\......\init_design.pb
...\.......\............\......\ISEWrap.js
...\.......\............\......\ISEWrap.sh
...\.......\............\......\opt_design.pb
...\.......\............\......\place_design.pb
...\.......\............\......\project.wdf
...\.......\............\......\route_design.pb
...\.......\............\......\rundef.js
...\.......\............\......\runme.bat
...\.......\............\......\runme.log
...\.......\............\......\runme.sh
...\.......\............\......\usage_statistics_webtalk.html
...\.......\............\......\usage_statistics_webtalk.xml
...\.......\............\......\vga.bit
...\.......\............\......\vga.dcp
...\.......\............\......\vga.tcl
...\.......\............\......\vga.vdi
...\.......\............\......\vga_1872.backup.vdi
...\.......\............\......\vga_2672.backup.vdi
...\.......\............\......\vga_3956.backup.vdi
...\.......\............\......\vga_clock_utilization_placed.rpt
...\.......\............\......\vga_control_sets_placed.rpt
...\.......\............\......\vga_drc_routed.pb
...\.......\............\....