搜索资源列表
visco_beam
- UMAT, FOR ABAQUS/STANDARD INCORPORATING ELASTO-VISCOPLASTICITY WITH LINEAR ** ** ISOTROPIC HARDENING. LARGE DEFORMATION FORMULATION FOR PLANE STRAIN ** ** AND AXI-SYMMETRIC ELEMENTS. IMPLICIT INTEGRATION WITH INITIA
visco_imp
- UMAT, FOR ABAQUS/STANDARD INCORPORATING ELASTO-VISCOPLASTICITY WITH LINEAR ** ** ISOTROPIC HARDENING. LARGE DEFORMATION FORMULATION FOR PLANE STRAIN ** ** AND AXI-SYMMETRIC ELEMENTS. IMPLICIT INTEGRATION WITH INITIAL
axi4lite_vip
- axi protocol verification tool
xapp740_axi_video
- High-Performance Video with the AXI Interconnect
AMBA
- AMBA 协议是用于连接和管理片上系统 (SoC) 中功能模块的开放标准和片上互连规范。它有助于首次开发带有大量控制器和外设的多处理器设计。AMBA 通过使用 AXI、AHB、APB 和 ATB 的规范对 SoC 模块的共同主干进行定义，这有助于设计的重复使用。-AMBA protocol is used to connect and manage on-chip (SoC) functional modules of open sta
axi_master_latest.tar
- RobustVerilog generic AXI master stub源码，包括文档说明-RobustVerilog generic AXI master stub
IHI0022D_amba_axi_protocol_spec
- this a standard of AMBA about AXI 4-lit and AXI-this is a standard of AMBA about AXI 4-lit and AXI
Axi
- 好看的网站模版 -Good-looking website templates
AMBA_AHB.rar
- amba AHB coding in verilog HDL and integrating with AHB to AXI Brigde,amba AHB coding in verilog HDL and integrating with AHB to AXI Brigde
AXI_MIG
- ISE生成的AXI接口的MIG，内存控制器，语言：verilog-ISE generated the AXI interface MIG, memory controller, language: verilog
eetop[1].cn_axibusregslice
- axi总线读写通道插入一级寄存器模块verilog源码,已验证- a slave interface is simple to achieve, need to look at
axi_slave_latest.tar
- AXI is AMBA4 compliant. code this code is a verilog imp lementation of AXI slae
demo_axi3_memory
- axi, ahp, app, verilog, integarader
src
- AXI Slave codes in verilog. Downloded from www.opencores.org free download
AMBAaxi-version-1.0
- this amba axi version 1.0-this is amba axi version 1.0
verilog-master-files
- Verilog master files of AMBA axi interface
merged_document
- report of amba axi.Also icludes samples
ds
- AXI protocal..used to check axi dut
Lab01-Creating_Embedded_System_13_1_1
- xilinx fpga microblaze Creating an AXI-based Embedded System
std_ovl_v2p7_Feb2013
- 目前最新的OVL库，里面是标准的ASSERTION模块，支持VHDL刚Verilog，最近在做AXI协议验证的时候用到，分享下-The latest OVL(open verification library),including all standard module of assertions(VHDL and Verilog). It can be used into AXI Protocl Verification. Just