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FPGA-CPLD_DesignTool(5-6)
- FPGA-CPLD_DesignTool(example5-6),需要的朋友可以下载-FPGA-CPLD_DesignTool (example5-6), a friend in need can be downloaded
FPGA_DDS
- 基于FPGA＋DDS的MSK数字调制源设计 通信中的DDS技术应用-FPGA+ DDS MSK modulation source design communication of DDS technology
key
- 一个4*4矩阵键盘的VERILOG接口程序设计（FPGA）-A 4* 4 matrix keyboard interface program Verilog Design (FPGA)
dds_quicklogic
- 这是quicklogic公司的直接频率合成（DDS）Verilog代码-QuickLogic Corporation This is a direct frequency synthesizer (DDS) Verilog code
DDs
- 此为DDS的单片机程序，已经得以实现，请放心。-This is the single-chip DDS procedures, has been able to realize, please rest assured.
EXPT84_DAC2ADC
- FPGA+DA转换,ALTERA公司FPGA与DA实现,DA转换功能!-FPGA+ DA conversion, ALTERA company FPGA and DA realize, DA conversion!
NIosIIStart
- NIosII软处理器快速入门,ALTERA FPGA的NIOSII入门指导-Quick Start NIosII soft processor, ALTERA FPGA s NIOSII Getting Started guide
fenping
- FPGA里面的分频器相关资料-FPGA divider inside information
DDS-320-func
- 在采用 320x240 屏的设计实验箱上运行，产生正弦波，调幅调频波形，扫频。
ddswase
- dds信号发生器，可以产生任意频率的正弦波，发波和谐波.已经编译通过-dds signal generator, can generate any frequency of the sine wave, the waves and harmonics. has been compiled through
DDS
- DDS的频率转换可以以近似认为是即时的，这是因为它的相位序列在时间上是离散的，在频率控制字改变之后，要经过一个时钟周期之后才能按照新的相位增量增加，所以也可以说它的频率转换时间就是频率控制字的传输时间，-DDS frequency conversion can be considered similar to real-time, this is because it is the phase sequence in time is d
dds
- 基于FPGA的双路可移相任意波形发生器 Altera中国大学生电子设计文章竞赛获奖作品刊登-FPGA-based dual phase shifter can be arbitrary waveform generator Altera China Undergraduate Electronic Design Contest winning entries published articles
DDS
- DDS原理介绍，里面是有时序图和系统设计！-DDS principle that there is a timing diagram and system design!
dds
- dds移相信号发生器 VHDL语言代码-dds
32_hottest_forum_CPLD-FPGA
- 收集了目前关于FPGA设计的论坛，大家如果有什么疑问，可以到这些论坛上求助。-The collection of the current design of the forum on the FPGA, there is little doubt if the U.S. can go to for help on these forums.
dds
- dds算法的fpga实现 altera 根据不同设置，输出不同频率的信号源-dds algorithm to achieve fpga set according to different altera, the output of the signal source at different frequencies
FPGA-basedhigh-performance32-bitfloating-pointnucl
- 基于FPGA的高性能32位浮点FFTIP核的开发，适合fpga工程技术人员参考-FPGA-based high-performance 32-bit floating-point nuclear FFTIP development, engineering and technical personnel for reference fpga
DDS
- Quartus中实现的DDS 使用的是altera提供的IP core-DDS achieved Quartus using IP core provided by altera
VIDEO-FPGA
- 视频采集输出实例，FPGA视频采集和输出-Video Capture output examples
FPGA
- 为了满足科研与实验需要,提出并实现了一种以FPGA和高速D/A为核心,其结构简单,控制灵活,信号质量高的多功能信号源生成系统。该信号源生成系统能够实时产生中心频率在30~130 MHz的各种雷达、通信、导航和白噪声等信号,且产生的各种信号频率、幅度、相位和其他参数均可控。信号源作为基带信号单元配以混频模块,可实现在任意频段的信号。另外,该信号源还可以作为一个通用平台,通过FPGA内部程序的更新来实现其他复杂信号。-This paper