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TriStepperDriveFinalUsbRfNo127CharBlow2
- control 3 stepper motors simultaneously, with FSM connection for LabVIEW interface and other high level application to call. control 3 stepper motors simultaneously, with FSM connection for LabVIEW interface and other h
jtag fsm
- jtag接口的状态机实现，李庆华《通信IC设计》随机代码(State machine implementation of JTAG interface)
ahb_fsm
- AMBA AHB design code.rar
spi_MasterSlaver
- 实现3种模式SPI主从模块功能设计，数据位宽8bit，最大SPI时钟频率支持112MHz，采用FSM设计实现。经本人亲测可用，使用于Spartan6——45T系列芯片；(To achieve three modes SPI master and slave module function design, data bit width 8bit, the maximum SPI clock frequency support 112MHz
FSM
- material regarding finite state machine
TrafficFSM
- runs on tm4c123 CodeComposerStudio finite state machine using C
simple FSM0
- simple implemenation of FSM in VHDL
Car_Tester
- 检测出入口车辆进出情况，显示停车位空余数量，FSM，带消除干扰处理(Check out the import and export situation of the entrance vehicle, show the number of parking space spare, FSM, with the elimination of interference treatment)
project_FSM
- Finite State Machine in VHDL
machine
- Simple finite state machine on Altera Cyclone II
testSta状态机对应代码
- 有限状态机又称有限状态自动机，简称状态机，是表示有限个状态以及在这些状态之间的转移和动作等行为的数学模型。它反映从系统开始到现在时刻的输入变化，转移指示状态变更，并且用必须满足来确使转移发生的条件来描述它；动作是在给定时刻要进行的活动的描述。(Establish basic finite state machine)
dayashankar_nair_verilog_2.1.tar
- finitie strate machine
dayashankar_nair_verilog_2.2.tar
- finite state machine
FPGA_flash设计
- 我们的设计是用一个FSM控制器来控制发送什么命令，flash模块判断FSM发送过来的state信号来选择应该执行什么操作，当命令写入或者读出后，会发送一个flag_done命令，这个命令让我们判断上个指令是否完成，如果完成后FAM将发送下一个命令.(Our design uses a FSM controller to control what commands are sent. The flash module judges the
FSM for controller
- a verilog code for energy harvesting controller
LAB
- SAM VHDL编码，包括数据选择器，加法器，简易逻辑电路，有限状态机等(FSM SAM ALU and many other different parts)
FSM_design using Verilog
- FSM verilog (Mealy and moore)