搜索资源列表
8b10b_encdec_latest.tar
- 8b10b编码的FPGA ipcore, 8b10b编码的FPGA ipcore-The 8b10b encoding of FPGA ipcore of 8b10b coding-FPGA ipcore, 8b10b coding the FPGA ipcore of
mini2440_manual
- he code allows lm3s9B96 chip thr JPEG encoder for ARM cortex M3 LPC11u14 chip system clock driver USB device chip LPC11u14 mass sto Based stm32f103vet6 and vs1003 mp FM1702 The classic example of embed
frequency_measuement
- 通过基4-fft算法测128点频率模块,其中包含所有需要的vhd文件，但是由于最多100M内容，因而需要用到的ipcore需自己添加。-128 points frequency measurement through based4-fft method,the folder involves all .vhl file,but it don t involves the ipcore due to the100M limit.
Ma-baker7
- This corde generate Baker signal user DDS ipcore
STM32
- 李想STM32视频教程 智芯STM32开发板全套资料-Lee wanted STM32 video tutorials IPCore STM32 development board complete information
jpegencode_latest.tar
- fpga verilog 实现jpeg ip核编码器-fpga verilog forjpeg encode ipcore
expand
- 用VHDL语言实现屏幕保护程序，用IPcore储存衣服图像-Just as
Syn_FIFO(wanzheng)
- 基于IPcore的同步FIFO的编写。读写数据位宽都为8bit，深度为32.-Based IPcore synchronous FIFO preparation. Read and write data width are 8bit, a depth of 32.
synchoronous_FIFO(jianban)
- 基于IPcore的同步FIFO的设计。采用Verilog代码书写。读写位宽均为8bit，深度为32.-IPcore synchronous FIFO-based design. Using Verilog code writing. Read and write bits wide are 8bit, depth is 32.
sram_IS61LV25616AL
- sram的ipcore 是用vhdl写的 但是不连接三态桥-the ipcore of the sram
ddr2_mem
- DDR2 xilinx ipcore 头文件 可以进行读写DDR2操作的接口! 读写时注意 按照时序控制进行！-DDR2 xilinx top file， you can read or write DDR2 interface。 attention：please control it ！
adder_26
- 加法器 IPcore调用，如何添加调用，应该是26位的-Adder IPcore call, how to add call, it should be 26-bit
fft-IPcore
- verilog编写，基于ISEfft的ip核研究，数据生成采用matlab，有仿真截图-verilog written, ip nuclear research ISEfft based on data generated using matlab, there are simulation screenshot
new1
- 基于MSP430FR3596单片机写的CYRF6936无线模块程序。（智芯锐电子论坛：http://www.zhixinrui.com）-Based MSP430FR3596 MCU write CYRF6936 wireless module program. (IPCore Sharp Electronics Forum: http://www.zhixinrui.com)
priyamka_madam
- THINS TO REMEMBER BEFORE IPCORE
Xilinx_DDR2_IP_TEST
- 本文档对Xilinx 公司FPGA开发环境中ISE中如何调用DDR2 IP进行了详细的说明。直接例化IPCORE,采用无TESTBENCH，无PLL的方式.-This document FPGA from Xilinx ISE development environment how to call DDR2 IP for a detailed descr iption. Direct instantiation IPCORE, no-T
IPcore
- verilog IP核调用子程序，源码-Verilog IP core call subroutine, the source code
FPGA4JIIR
- 常用的数字滤波器有FIR数字滤波器和IIR数字滤波器｡ FIR数字滤波器具有精确的线性相位特性,在信号处理方面应用极为广泛,而且可以采用事先设计调试好的FIR数字滤波器IPCore来完成设计,例如Altera公司提供的针对Altera系列可编程器件的MegaCore,但是需要向Altera公司购买或申请试用版｡ 另外,对于相同的设计指标,FIR滤波器所要求的阶数比IIR滤波器高5~10倍,成本较高,而且信号的延迟
demo4
- AXI4-stream协议，用于调试，测试代码，IPcore-The AXI4-stream protocol, used to debug, test code, IPcore
fft-ip-core
- 通过调用ISE中的fft IPcore实现了fft计算，输入数据通过textio从文本文件读入，处理后的数据再读入文本中。由于数据精度问题，与MATLAB计算的结果存在一定的误差-By calling the ISE of FFT IPcore implements the FFT computation, the input data through textio read a text file, after processing