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mii-diag.tar
- Linux下通过mii接口控制网卡的工具-Linux with MII interface card control tools
mii
- 以太网PHY端口MII物理层收发程序，可作为开发参考
Mii
- 以C语言利用PIC12C508A读写MII Phy的寄存器-to use C language literacy PIC12C508A MII Phy register
smii-to-mii
- SMII 到 MII 转换的VHDL代码
mii to rmii代码
- mii 接口转rmii接口的verilog代码
mii设计详解
- mii接口的详细讲解
mii接口
- 以太网知识MII接口：本文主要分析MII/RMII/SMII，以及GMII/RGMII/SGMII接口的信号定义，及相关知识，同时本文也对RJ-45接口进行了总结，分析了在10/100模式下和1000M模式下的设计方法。
mii-diag.tar
- Linux下通过mii接口控制网卡的工具-Linux with MII interface card control tools
Mii
- 以C语言利用PIC12C508A读写MII Phy的寄存器-to use C language literacy PIC12C508A MII Phy register
FEnetPQ2
- MPC8260的Fast Ethernet的例子。配置FCC为Fast Ethernet模式，然后接MII口。用标准C语言编写。-MPC8260 Fast Ethernet example. FCC configuration for Fast Ethernet model, then the MII mouth. Using standard C language.
miiDriver
- 单片机读写MII寄存器驱动，包括初始化，单字符的读写，定长度字符的读写。-SCM reader MII register drives, including initialization, single-character reader, determining the length of written characters.
eathnet
- 百兆以太网mac和mii的vhdl源程，作IPcore的时候非常有用-Fast Ethernet MII and the VHDL source way for IPcore very useful when
Micrium_PHY_KSZ8721BL
- 该程序用C++实现了KSZ8721以太网接口驱动包括： 1、支持 Micrel KSZ8721BL PHY. 2、MII interface port是 EMAC。 3、实现了通过EMAC以太网接口读写书数据。-The procedure used C++ Realize the KSZ8721 Ethernet interface drivers include: 1, support Micrel KSZ8721BL
ethernet_tri_mode_rtl.tar
- 以太网控制器verilog，含有mac,mii接口-Ethernet controller verilog, containing mac, mii interface
linkstate
- linux 上读网卡mii寄存器判断网卡连接状态-linux read NIC card mii registers to determine the connection status
mii
- 以太网PHY端口MII物理层收发程序，可作为开发参考-MII Ethernet PHY port physical layer transceiver procedures, can be used as the development of reference
MIIinterface
- MII接口1转2处理，可以实现在serdes上方便传输MII。-MII interface 1 to 2 treatment can be achieved in the serdes to facilitate transmission MII.
smii-to-mii
- SMII 到 MII 转换的VHDL代码-SMII to MII conversion of VHDL code
MII
- MII接口编程,用于收发以太网MAC帧的FPGA实现。-MII interface programming, send and receive Ethernet MAC fr a me for the FPGA.
MII
- 以太网MII芯片配置接口的VHDL设计，配置PHY芯片的模块设计-Ethernet MII chip configuration interface VHDL design, configuration PHY chip module design