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reversalBW64_7.10
- 在ccs中调试DSP外部存储sdram的反色代码，主要是通过dsp/bios中的HST管道实现的。其中选用的是DM642芯片及MT48LC16M16A2的sdram，且sdram的相关时序参数已配置好。
reversalBW64_7.10
- 在ccs中调试DSP外部存储sdram的反色代码，主要是通过dsp/bios中的HST管道实现的。其中选用的是DM642芯片及MT48LC16M16A2的sdram，且sdram的相关时序参数已配置好。-In ccs debug DSP external memory sdram of the anti-color code, mainly through the dsp / bios in the HST pipeline imple
mem_ctrl
- memory control source code
mt48lc16m16a2
- SDram 接口verylog 程序 SDram 接口verylog 程序-SDram interface procedures verylog
mem_ctrl
- memory very useful free core
SDRAM_VerilogCode
- 基于FPGA的SDRAM控制器Verilog代码，开发环境为Quartus6.1，控制SDRAM实现对同一片地址先写后读。-FPGA-based SDRAM controller Verilog code, development environment for Quartus6.1, control of SDRAM to achieve the same address one after the first time to wri
SDRAM
- SDRAM控制器，Verilog代码编写，让你快速了解SDRAM的读写时序。包含Modelsim仿真工程和学习笔记-SDRAM controller, Verilog coding, allows you to quickly understand the SDRAM read and write timing. Modelsim simulation engineering and contains study notes
MT48LC16M16A2
- System will automatically delete the directory of debug and release, so please do not put files on these two directory.
MT48LC16M16A2
- 硬件芯片MT48LC16M16A2的说明书 硬件芯片MT48LC16M16A2的说明书-The manual hardware chip MT48LC16M16A2