搜索资源列表
异步通信控制器
- 用VHDL语言编写的异步通信控制器源代码程序-ASCC Communication Control System Compiled With VHDL
core_arm.tar
- 用VHDL语言实现的ARM处理器的标准内核的源代码程序，可在重用-use of the VHDL standard ARM processor core source code procedures, the reuse
100Examples
- 100个VHDL语言示例源代码
CPU设计
- 用VHDL设计的一个16为CPU，内有开发文档以及源代码
sdRAM设计及源代码（vhdl）
- 通过对不读数据的不断刷新来保持数据，通过地址线复用来传输数据。
quanjiaqi
- 全加器的详细设计思路和用VHDL语言编写的详细源代码-increase for the whole of the detailed design ideas and the use of VHDL for preparing a detailed source code
DDFS_1
- 主要介绍DDFS的主要结构，和它的实现方法还有源代码（VHDL）-introduces the main structure and the implementation methods have the source code (VHDL)
Xilinx-modelsim-library
- Xilinx的modelsim 仿真库！里面有许多库函数，对于ｖｌｏｇ或ｖｈｄｌ编程有很多好的源代码可以剪切！-Xilinx modelsim simulation library! There are many libraries, vlog or VHDL programming a lot of good source code can shear!
8051VHDLyuandaima
- 这是用C语言编写的关于8051的VHDL的源代码-This is the C language on the preparation of the 8051 VHDL source code
26_1000
- 若干VHDL语言的源代码，我觉得应该用用仅供参考-several VHDL source code, I think that should be used for reference purposes only
lifang_VHDL
- 该代码是实现函数的立方源代码，用VHDL写的，在软件上已经用过了-code is the function of the cube source code, written in VHDL, the software has been used on the
veoghdl
- 用VHDL语言编写的异步通信控制器源代码程序 -VHDL language of asynchronous communication controller source code procedures
UP3_CLOCK2
- UP3开发板上的时钟控制源代码文件，VHDl编写-degrading development control board clock source documents, prepared VHDl
VHDL_block
- 这是关于VHDL模块的源代码，欢迎大家下载使用。-This is the module on the VHDL source code, welcomed the U.S. download.
sport_CAD
- 这是关于VHDL运动表状态机的源代码，欢迎大家下载使用-This is the Sport on the state machine VHDL source code, welcomed everyone to download use
ttyscz
- 运用vhdl语言编程,是数字逻辑中的电子钟!各模块及源代码都有,适合电信同学使用!-The use of VHDL language programming, digital logic electronic bell! Various modules and source code are suitable for the use of telecommunications classmates!
Cpld
- atmel公司arm926 开发办cpld源代码vhdl写的， 供大家参考-Atmel CPLD Development Office Company ARM926 VHDL source code written for your information
vhdl2
- vhdl语言的程序基本结构，很有用的资料，结好了很多程序源代码-VHDL procedures for the basic structure of language, very useful information, a lot of good binding source code
ata.tar
- 使用verilog和VHDL两种硬件描述语言实现了一个ATA硬盘控制器，包括源代码、测试仿真文件和说明文档-The use of two types of Verilog and VHDL hardware descr iption language to achieve an ATA hard drive controller, including source code, testing, simulation files and
Counter
- VHDL硬件描述，使用环境为Quartus2 6.1 分别为16进制及60进制计数器的源代码-VHDL hardware descr iption, the use of the environment Quartus2 6.1, respectively, for 16 M and 60 M-ary counter source code