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speex-1.0.5.tar
- 一个非常好的开源音频编解码项目，支持多种音频采用频率，支持多码流，支持可变速率 Speex a free codec for free speech Speex is an Open Source/Free Software patent-free audio compression format designed for speech. The Speex Project aims to lower the barrier o
speex-1.0.5.tar
- 一个非常好的开源音频编解码项目，支持多种音频采用频率，支持多码流，支持可变速率 Speex a free codec for free speech Speex is an Open Source/Free Software patent-free audio compression format designed for speech. The Speex Project aims to lower the barrier o
altera_lwip
- 已移植到altera nios ii软核的基于microC/OS操作系统的lwip全套源代码- Transplanted to altera the nios ii soft nucleus based on microC/OS the operating system lwip complete set source code
altera+dpd
- 数字预失真在通信领域内IP核的开发文档，包括数学表达式及硬件框图-Digital Predistortion in the field of IP communications in the development of nuclear documents, including mathematical expression and hardware block diagram
imgconv
- lcm显示功能，用于单片机与嵌入式应用系统。可自由显示图形和文本。-LCM display function for the single-chip and embedded applications. Be free to display graphics and text.
uart_IP
- altera 的uart ip核，可直接调用 在quartus中把库指向文件位置就可-altera the uart ip nuclear, can be directly called in the Quartus point in the database file location can be
16550
- UART16550兼容的串行通讯控制器，Verilog语言描述，采用Altera Cyclone系列芯片实现FPGA综合，因为FIFO部分利用到内部资源实现。已经在某项目中成功应用，特此推出。-UART16550 compatible serial communication controller, Verilog language descr iption, the use of Altera Cyclone series FPGA
RS232
- 基于VHDL的RS232通讯程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用-VHDL based on the RS232 communication procedures, including complete source code, locking pin, as well as download files documents can be directly downloaded using
zbt_rd_vhdl_str_v1.0.0
- ddr2 controller功能控制,里面有四个模块-ddr2 controller functions to control, which has four modules
Terasic_Blaster_Loader
- usb-Blaster 93c46烧写工具-usb-Blaster 93c46 programmer tools
altera_modelsim
- 比较详细的总结，个人花了一天写的，很好的哟-A more detailed summary, individuals spent a day writing, good yo
pci
- altera pci license al tera pci license -altera pci license al tera pci license
ug_alt_ufm
- ALTERA公司的MAXⅡ系列CPLD的内部flash使用教程，内容很详细，图文并茂，英文版。-ALTERA s MAX Ⅱ series CPLD to use the internal flash tutorial is very detailed, with illustrations in English.
FIFO_EMIF
- 实现FPGA通过EMIF总线给DSP定期发送数据的功能-FPGA implementation through the EMIF bus regularly send data to the DSP function
SPI_IIC_design_example
- ALTERA原厂提供的例程，网上很难找到的，在MAX2系列芯片上实现过，VHDL和VERILOG两种语言编写 IIC读写程序-ALTERA provided the original routine, it is difficult to find online and in the MAX2 series chip-off, VHDL and VERILOG two languages
Altera_DE1_Training_Courses_Multimedia_Platform.zi
- Altera DE1 多媒体平台训练课程 视频教程-Altera DE1 training courses multimedia platform Video tutorial
ram
- 使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上用硬件描述语言实现一个RAM存储器。-The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board with hardware descr iption language to ach
altera_fft
- alter官方fft程序 使用verilog编写 需要的同学可以下载-alter the official fft program uses verilog prepared students in need can be downloaded
altera_modelsim
- modelsim6.0—altera 详细的教程，肯定能教会你，比网上那些好多了，分享给大家-good！