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SSD6-Exercise5
- SSD6(系统级编程)的Exercise 5: Cache Lab,自己做的,满分。 -SSD6 (system-level programming) the Exercise 5: Cache Lab, own, and out of.
spim-Setup
- spim-cache 模 拟 器 安 装 程 序-spim-cache simulator setup
pingpang
- 关于乒乓操作的,对于数据缓存有很大的用处-On the ping-pong operation of data cache for the great usefulness of
LZZQ
- Compression speed ~= Decompression speed. (around 200-300 MB/s) CPU notes: LZZQ uses 32KB dictionary, reduce to 16KB (change HASH_SIZE to 4*1024) for good L1 cache access (with little reduction in ratio).
tilecache-2.10.tar
- 切片程序,完成类似googole map的地图图片缓存功能-Biopsy procedures, to complete a similar picture googole map cache of map features
simulator
- It is a cache simulator for L1 and L2
gaobingfawangzhanjiagou
- 高并发高流量网站架构知识集合: 架构考虑问题; 负载均衡; 服务器优化; 数据库优化; cache技术:oscache/memcache/ehcache java优化等-High-concurrency fr a mework for high-traffic Web site of knowledge set
GetVistaCacheResource
- 批处理提取缓存文件(vista) - 从注册表里提取的缓存目录-Batch extraction of cache file (vista)- extracted from the registry in the cache directory
tracecache
- Trace cache simply guideline here.
Connguration_and_Coding_of_Cache_in_VxWorks_operat
- 摘要:该文提出了一种合理地应用Cache的方法,以解决VxWorks环境下操作系统的启动速 度慢和应用程序运行效率低的问题。在启动过程中,通过修改配置文件来合理地打开代码 Cache和数据Cache,加快操作系统的启动速度;在应用程序开发过程中,通过使用不同的Cache 编程方法,提高应用程序的运行效率。实例分析给出了具体应用的实现方法。 关键词:VxWorks操作系统;高速缓冲存储器;直接存储器存取-Abstract:
JRE.Cache2.0
- Make your Joomla and Mambo website 100 times or more faster. Increase now the performance of your website with the Joomla accelerate component. The Joomla performance accelerate component will boost the performance of yo
smartycache
- smarty cache 代码 说明 代码 例子-smarty cache source code examples that
cpufunc
- arm cache/TLB invalidate and flush code
cameralink
- 由于目前基于CameraLink接口的各种相机都不能直接显示,因此本文基于Xilinx公司的Spartan 3系列FPGAXC3S1000-6FG456I设计了一套实时显示系统,该系统可以在不通过系统机的情况下,完成对相机CameraLink信号的接收、缓存、读取并显示 系统采用两片SDRAM作为帧缓存,将输入的CameraLink信号转换成帧频为75Hz,分辨率为1 024×768的XGA格式信号,并采用ADV7123JST芯片实现数
DistributedCacheDemo
- 分布式缓存源码-包含memcached存储方案-Distributed Cache Demo
software-cache
- Cell 处理器中SPE上的软件管理缓存代码-software managed cache code on Cell BE processor
cache1
- * This example demonstrates how to switch L2 CACHE mode at run-time. -* This example demonstrates how to switch L2 CACHE mode at run-time.
dCACHE
- Vhdl写的数据cache,根据Verilog程序改编-Vhdl write data cache
iCACHE
- 用VHDL写的数据cache,基于Verilog版本改编过来-To use VHDL to write the data cache, based on the Verilog version of the adaptation over
simulator
- 开源的基于SystemC的模拟器,可以模拟ARM CPU, Cache, DDR,NOR, NAND, 时序和功耗均可以正确模拟。-This simulator is a cycle-accurate system-level energy and timing simulator. Developed by Embedded Low-Power Laboratory, Seoul National University. The si