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counter
- program of counter using command force clk 1 50, 0 100 -repeat 100 -program of counter using command force clk 1 50, 0 100-repeat 100
counter
- 用php实现的一个计数器程序 可以变成多重的计数器-Php achieved with a counter can be turned into a multi-program counter
Pulsecount
- 脉冲计数，脉冲输入，脉冲上跳沿计数器加一，周期脉冲输入-Pulse count, pulse input, pulse on the jump along the counter plus one cycle pulse input
jc2_ver
- Johnson counter with verilog
pulse_counter
- AVR MEGA8 Pulse Counter Proteus
Counter
- Controled counter delphi
counter
- 利用EDA工具MAX-PlusII的VDHL输入法，输入VHDL程序，实现2位计数器，在七段译码器上以十进制显示：0、1、2、3、0、...。时钟信号使用83管脚。采用自动机状态转换方式设计该计数器；建立相应仿真波形文件，并进行波形仿真；分析设计电路的正确性。-The use of EDA tools VDHL of the MAX-PlusII input method, enter the VHDL program, the rea
counter
- 用C语言编写的通讯录程序，谢谢，希望可以！-counter used of c language
CarCounting
- Car counter application in opencv
UpDownCounter
- 8-Bit Up Down Counter Verilog Code
counter
- 计数器可以进行行与列同时计数 -counter
RPM_counter
- controller based RPM counter
counter
- 实现了各种精度的计算器，可供学习，也可应用的工程中。- the difference counter ,it can help to learn VHDL ,it can also be as a modular in your project
counter.tar
- 基於verilog 所製成的counter程序，可以向上計數-Verilog made based on the procedures of the counter can count up
counter
- 使用临界区机制同步线程，假如一个银行系统有两个线程执行取款任务。一个使用存折在柜台取款，一个使用银行卡在ATM取款。若不加控制，很可能账户余额不足于两次取款的总额，但还可以把钱取走。-Critical mechanism for the use of thread synchronization, if a banking system there are two threads to implement task teller. A
COUNTER
- MSDN的经典例子+连接 COUNTER.rar-COUNTER.rar
IR_USEING_TERRUPT
- IR using interrupt 0 read ir code and use timer0 counter-IR using interrupt 0 read ir code and use timer0 counter
CheckMultiprocessor
- vc6.0 程序 展示了如何用WMI的方法获取CUP的使用率 重点在于获取多个CPU或者多核不同的使用率,在现在CPU多核时代这点很重要-Ever since I saw Performance application on Windows 2000, I wondered if there is a way/Windows API to programmatically determine CPU usage for ea
Counter
- A simple java source line counter. Found it on google.
Ripple_Carry_counter
- Ripple Carry Counter. the synchronous version of Ripple Counter. a bit less fasr version the ripple counter but a synchronmous one that will work well on FPGA. wrriten in behavioral VHDL.