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fifo
- fpga中fifo的基本原理介绍了fifo的基本原理以及对fifo实现方法的阐述。-The basic principle in fpga fifo fifo introduced the basic principles and methods of implementation described fifo.
FX2-Slave-FIFO
- 最常用的USB数据采集系统 CY7C68013 SLAVE FIFO 模式 不需要修改，已验证过-The most common USB data acquisition system CY7C68013 SLAVE FIFO mode does not change, has been verified
Verilog_CY7C68013-SLAVE-FIFO
- 用VERILOG 编写 CY7C68013 usb数据采集SLAVE FIFO模式驱动程序 ，已验证过-Prepared with the VERILOG CY7C68013 usb data acquisition SLAVE FIFO mode driver, has proven
FIFO
- 运用Verilog 语言对FPGA实现同步的FIFO的数据缓存和传输功能。-FPGA Verilog language used to synchronize the FIFO data buffer and transmission functions.
Asynchronous-FIFO-design
- 异步FIFO是一种先进先出的电路，在异步电路中，由于时钟之间周期和相位完全独立，因而数据丢失概率不为零。如何设计一个高可靠性、高速异步的FIFO是一个难点，本代码介绍了一种解决方法。-Asynchronous FIFO is a kind of advanced first out circuit, in asynchronous circuit, as the clock cycle and phase between full in
fifo-VerilogHDL
- 利用VerilogHDL语言编写的同步FIFO，异步FIFO的编写及其注释-VerilogHDL language using synchronous FIFO, asynchronous FIFO, write and comment
cy7c68013-Slave-FIFO
- cy7c68013 slave fifo fw
fifo
- verilog实现fifo，ise中仿真，chipscope调试-verilog achieve fifo, ise in the simulation, chipscope debugging
FIFO
- 基于fpga的fifo的设计与实现，好东西，希望大家喜欢-Fpga-based design and implementation of fifo, good things, hope you like
FIFO-LRU-OPT-Clock
- 页面置换算法，FIFO，LRU，OPT，NUR。-Page replacement algorithm
fifo
- Verilog HDL实现复杂逻辑设计FIFO-Verilog HDL to achieve FIFO
fifo
- 详细介绍了fifo深度计算的方法，fifo深度的计算是面试中常被问到的问题！-Fifo depth details of the method of calculation, fifo depth calculation is frequently asked interview questions!
quartusII-FIFO
- 教你如何用QuartusII软件设计FIFO-us QuartusII design FIFO
FIFO Design
- 异步fifo设计经典文章，可作为异步fifo设计基础导读(Asynchronous FIFO design classic article, can be used as the basis for asynchronous FIFO Design Guide)
fifo
- 一个简单的FIFO实现，基于STM32的UART+DMA方式。(A simple FIFO implementation, based on the STM32 UART+DMA approach.)
fifo
- 异步FIFO 输入: 16bit 输出:16bit 深度:256(Asynchronous FIFO Input: 16bit Output: 16bit Depth: 256)
FIFO
- 用verilog语言的实现FIFO存储器，以先进先出的方式处理数据(The FIFO memory is implemented in Verilog language, and data is processed in FIFO)
Synchronous FIFO
- 用16*8 RAM实现一个同步先进先出（FIFO）队列设计。由写使能端控制该数据流的写入FIFO，并由读使能控制FIFO中数据的读出。写入和读出的操作由时钟的上升沿触发。当FIFO的数据满和空的时候分别设置相应的高电平加以指示(mplementation of a synchronous first in first out (FIFO) queue design with 16*8 RAM. A write FIFO that con
FIFO
- FIFO的功能众所周知，非常好的处理时序问题。(The functions of FIFO are known to be very good at dealing with timing problems.)
SCI.fifo
- DSP2812SCI通信程序，采用 fifo模式(DSP2812SCI communication procedures, using fifo mode)