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or1200_sopc
- 用verilog语言编写的or1200+wishbone总线+串口uart+片上ram,最小系统soc。包括片上ram的软件系统(C语言编写)都有。但下载者要使用此系统需要很多工具链,搞soc的应该都装好了。 绝对原创!用quartusII11.0在Altera DE2-115上验证通过,Modelsim SE 6.5f仿真通过。-It s very strange for Chinese people communicating
SCMIPS
- 使用verilog代码描述了一种简单的单周期MIPS处理器实现,并在ModelSim SE6.5c调试通过。-The verilog code describes a simple, single-cycle MIPS processor implementation, and debugging through in ModelSim SE6.5c,.
Chapter2
- Chapter2文件夹:(1)Quartus II 8.0软件实例讲解:1位加法器实验,完整的设计工程文件在Chapter2/adder文件夹下(2)ModelSim SE 6.0软件实例讲解:十进制计数器实验,完整的设计工程文件在Chapter2/test_counter_10文件夹下 -Chapter2 folder: (1) the Quartus II 8.0 software examples to explain: an
RS232
- (6)实验6:串口通讯实验,完整的设计工程文件在RS232文件夹下二、运行环境 程序在以下环境调试通过: (1)Windows XP; (2)Altera公司的Quartus II 8.0 for windows; (3)Altera公司的Nios II 8.0 IDE for windows; (4)Mentor公司的ModelSim SE 6.0;-(6) (2) Altera Corporation
Serial-receiver
- 本实例中,开发板通过串口与PC上运行的上位机软件通信,使用了modelsim 定时器T0作为波特率发生器,串口波特率为9600。-In this instance, the development board communication through the serial port on a PC running PC software, use the timer T0 as a baud rate generator, ser
shft_reg
- 移位寄存器的VHDL语言实现,quartus 和 modelsim 仿真-Shift register VHDL language quartus and modelsim simulation
clock
- 数字计时器的vhdl实现,quartus 和 modelsim 仿真-Digital timer vhdl achieve quartus and modelsim simulation
Assignment-3
- Assignment 3 Construct VHDL models for 74-139 dual 2-to-4-line decoders using three descr iption styles, i.e., behavioral, dataflow and structural descr iptions. (1) Synthesize and (2) simulate these models respectively
16-bit-A-DCa16-bit-DAC-VHDL
- 16-bit Analogue to Digital Converter&16-bit Digital to Analogue Converter VHDL source code.在modelsim下仿真通过-16-bit Analogue to Digital Converter & 16-bit Digital to Analogue Converter VHDL source code. Simulated in m
sequence_detect
- 串行数据检测器,检测数据中是否存在10010,用FSM编写,在modelsim中仿真通过,功能上符合要求-Serial data detector detects data exists 10010, with FSM write, through simulation in modelsim functionality required
assigment3
- Construct VHDL models for 74-139 dual 2-to-4-line decoders using three descr iption styles, i.e., behavioral, dataflow and structural descr iptions. Synthesize and simulate these models respectively in the environmen
modelsim-sdram-sim
- 包括sdram 测试平台,sdram控制器,sdram行为模型。-Includes sdram testbench, sdram controller, sdram behavior model.
Altera_Modelsim
- Altera_Modelsim仿真资料,详细介绍modelsim的用法,希望帮到大家-Altera_Modelsim simulation data, modelsim usage details, hope to help everyone
S6_VGA
- 1。源文件保存在src目录,QII的工程文件保存在Proj目录; 2。程序实现的功能是在VGA显示器上显示彩色条纹,共8种颜色, 可以使用嵌入式逻辑分析仪观测信号; 3。modelsim仿真文件在proj--simulation--modelsim中-1. The source file is saved in the src directory QII project file is saved in the direc
S3_WAVE
- 1、本实验模拟正弦函数发生器 2、使用逻辑分析仪查看波形 3、/proj/simulation目录中可以在modelsim中仿真-1, the experimental simulation of the sine function generator, logic analyzer view waveform 3/proj/simulation directory in modelsim simulation
how-to-make-a-testbench
- 怎样写一个testbench 讲述了怎样在ise或者modelsim里面怎样写仿真测试-How to write a testbench about how how to write a simulation test in ise modelsim inside
clk
- 基于EP2C5Q208C的二分频verilog代码,modelsim仿真及下载配置-Verilog code, modelsim simulation and download configuration based on EP2C5Q208C binary frequency
digital-watch
- 这是一个电子表的完整工程,仿真工具是modelsim,综合工具是quartus,开发版是DE2.里面含有文档进行详细说明-This is a complete electronic table engineering, simulation tools modelsim synthesis tool is quartus Developer Edition is DE2 which contains documentation for
code
- 是用verilog写的带uart的简单controller,使用的是mips指令,用modelsim仿真,波形正确-With uart verilog write a simple controller, use the mips instruction the modelsim simulation, waveform correctly
scr
- 60进制计数器同步置位30异步复位 modelsim仿真代码含激励 自己写的 可用 仅供参考入门-60 binary counter 30 the asynchronous reset modelsim simulation code containing motivate yourself to write synchronization set can be used for reference only entry