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pcm_verilog
- 这是PCM电话传输系统模型的verilog程序,是一个modlesim开发环境下的工程文件,并有波形仿真结果.-PCM telephone transmission system Verilog model of procedures is a modlesim development environment under the project documents, and a waveform simulation results.
pcm_verilog
- 这是PCM电话传输系统模型的verilog程序,是一个modlesim开发环境下的工程文件,并有波形仿真结果.-PCM telephone transmission system Verilog model of procedures is a modlesim development environment under the project documents, and a waveform simulation results.
shuzhijietiaoqu
- 基于FPGA的全数字调制解调器设计实例，包含有Matlab程序和Quartus程序-FPGA-based all-digital modem design example, contains the procedures and Quartus program Matlab
MIF_create
- MIF文件生成器 用于quartus II等软件的ROM表mif文件生成-MIF file generator quartus II software for the ROM table to generate mif file
128bitCLA
- 128位CLA 采用kogge-stone tree算法 经modlesim验证正确-128-bit CLA using kogge-stone tree algorithm as the right to verify modlesim
pn_generator
- FPGA实现pn发生器，Verilog代码实现，另带modlesim的仿真测试文件，很有价值。-FPGA realization of pn generator, Verilog code, and the other with the simulation test modlesim documents of great value.
softdrink
- 自动售货机verilog源码,含找零功能，通过Modlesim,leonardo仿真，综合-Vending machine verilog source
interleaver
- 交织编码器的verilog代码实现，此外有testbench和波形。-the verilog code for the interleave encoder, with the testbench code and waveform screen print.
ddsVHDL
- fpga设计dds实现调频 调相 调占空比 并用modelsim仿真成功-dds fpga vhdl
frequency-divider
- 基于Quartus2和Modlesim环境下编译顺利通过的分频器源程序代码-Source code compiled Quartus2, and Modlesim environment passed the divider
ledtest
- 数码管译码电路的测试程序，使用modlesim进行测试。该文件和led.rar配合测试使用，如果不需要测试，无需下载该文件。led.rar使用的是模块化设计，分为几个vhdl文件。-Digital decoding circuit test program, using modlesim tested. The documents and led.rar with testing, if you do not test, without
uart
- 一种串行uart接口的实现，可支持对种通信速率，modlesim仿真-Realizing serial uart interface, which can support a variety of communication speed, modlesim simulation
gray_counter
- 格雷码计数器实质包含了三个部分 格雷码转二进制、加法器、二进制转格雷码。通过quartus II 自带的Modlesim仿真验证了 能够实现二进制和格雷码之间的转换(Gray counter essence contains three parts, gray code to binary adder, binary gray code conversion. Modlesim simulation by quartus with II
key_filter
- 采用Verilog语言的编写按键防抖代码，并通过modlesim进行验证(Using the Verilog language to write key anti - chattering code and verify it by modlesim)