搜索资源列表
4_in_1
- 骏龙提供的最新quartus8.0的license，包括Quartus II 8.0，NIOS II 8.0（在Quartus II的license里面），DSP Builde 8.0，ModelSim-Altera 6.1g (Quartus II 8.0)，新Quartus II的license支持远程桌面访问的功能。
4_in_1
- 骏龙提供的最新quartus8.0的license，包括Quartus II 8.0，NIOS II 8.0（在Quartus II的license里面），DSP Builde 8.0，ModelSim-Altera 6.1g (Quartus II 8.0)，新Quartus II的license支持远程桌面访问的功能。-Cytech latest quartus8.0 the license, including the Quart
crack-81
- 最新QuartusII8.1的补丁，安装它的破解器，可以获得长期使用权-QuartusII8.1 the latest patch, install it to break, and access to long-term use rights
twice_freqencey
- 用Verilog直接完成倍频的算法,经过了quartus8.0的时序仿真-Verilog multiplier used directly to complete the algorithm, as a result of timing simulation quartus8.0
fft_VHDL
- 使用altra的quartus8.1作为开发环境，用硬件语言VHDL实现了fft的变化-Altra as quartus8.1 use the development environment, language VHDL hardware changes to achieve the fft
shuzi4
- 四位数字乘法器，在quartus8.0下仿真时序图 -mult4
Crack_QII81_FULL_License
- quartus 8.1 ipcore lic,包含ddr、ddr2、fir、nco-quartus 8.1 ipcore lic, with ddr, ddr2, fir, nco
2c8_lcd12864
- 用quartus8.1创建的基于ALter公司的EP2C8的12864液晶显示一幅画的完整工程文件。-Quartus8.1 created using the company' s EP2C8 based ALter liquid crystal display a picture of the 12864 complete project file.
Quartus8.1_licence
- A way to evalulate Quartus 8.1
VHDL-djdplj
- 基于VHDL语言的十进制等精度频率计的设计，采用VHDL语言，运用自顶向下的设计思想， 将系统按功能逐层分割的层次化设计方法，使用Quartus8.0开发环境，实现了频率计的设计。-VHDL language based on the decimal precision frequency meter, etc. The design, using VHDL language, the use of top-down design,
FPGA-VHDL-dengjingduc
- 本文介绍了基于VHDL语言的十进制等精度频率计的设计，采用VHDL 语言，运用自顶向下的设计思想，将系统按功能逐层分割的层次化设计方法，使用Quartus8.0开发环境，实现了频率计的设计。 -This article describes the decimal-based VHDL, and other precision frequency meter design, using VHDL language, the use o
shumaguan
- 基于数码管的蛇形灯程序设计，开发环境为quartus8.1，在开发板上实现。-LED lights on the serpentine design, development environment for quartus8.1, in the development of on-board implementation.
st_1
- 12位dac8413驱动 vhdl编写 quartus8.1测试通过-dac8413 vhdl drive
ipcore
- quartus8.0的LPM参数化宏模块ipcore应用-quartus8.0 the LPM parameterized macro module ipcore application
decoder
- 基本门电路和译码器试验，含quartus8.0工程，源码，仿真和详细操作步骤，适合初学者上手。-Basic gate circuit and decoder tests, including quartus8.0 engineering, source code, simulation and detailed steps for beginners to get started.
uart_receive_send_verilog
- 自己写的串口quartus8.0工程，串口收发virilog程序，在EP1C3T144C8芯片验证运行成功，时钟频率50Mhz，波特率115200.-Own write serial quartus8.0-engineering serial transceiver virilog program runs successfully verified, in EP1C3T144C8 chip clock frequency of 50M
test_access_rot_edit2
- This file is VHDL code. sram access code. device name is Atera cyclone2. in quartus8.1 webedition.
frequency_measure
- 简单实现数字频率计，开发环境：Quartus8.0-Simple digital frequency meter development environment: Quartus8.0
dutyfactor
- 可调占空比程序，开发环境：Quartus8.0-Adjustable duty cycle of program development environment: Quartus8.0
f_changed_sin_wave
- 用RAM实现频率可调正弦波发生器，开发环境：Quartus8.0-To frequency tunable sine wave generator development environment: Quartus8.0 using RAM