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5bit-adder-subtracter
- 5 bits 的加法器與減法器合併電路之原始程式製作
5bit-adder-subtracter
- 5 bits 的加法器與減法器合併電路之原始程式製作 -5 bits of the adder circuit combined with the subtraction of the original browser program production
Mars-EP1C6-F_code1
- 此包中为FPGA学习板中的基础实验代码.共包括8个实验源代码:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机和四位比较器.-In this package for the FPGA board to study the basis of the experiment code. A total of eight experiments, including source code: 8-bit prio
VHDL
- 本代码为用VHDL语言设计实现加法器、减法器、乘法器，并提供了模块图，进行了波形仿真。-This code is for the use of VHDL Language Design and Implementation of adder, subtracter, multiplier, and provides a block diagram carried out a wave simulation.
EDA1
- 完成一位二进制全减器的设计，采用文本输入法分别实现，分层设计，底层采用半加器和逻辑门实现。-Completion of a binary full subtracter design, implementation, respectively, using the text input method, hierarchical design, are based on half adder and logic gates.
subber
- 完成一位二进制全减器的设计，采用原理图输入法和文本输入法分别实现，分层设计，底层由半加器（也用原理图输入法）和逻辑门组成-Completion of a binary full subtracter design, the use of schematic and text input method input method were realized, hierarchical design, the bottom of the ha
hw1
- Using the schematic Design Entry Method, design a logic circuit that has two 2-bit inputs X and Y, a 1-bit input CinOrBin, and a 1-bit control input SubAddn. When the control input SubAddn is ‘0’, the logic circuit behav
hw2
- Using the VHDL Entry Method, design a logic circuit that behaves a 2-bit adder ( X + Y + CinOrBin ) with carry-in when the control input SubAddn is ‘0’ and behaves as a 2-bit subtracter ( X – Y – CinOrBin ) with borrow-i
ADDER
- .采用原理图输入法和文本输入法实现全减器，分层设计，底层由半加器（也用原理图输入法）和逻辑门组成； 2.给出此项设计的仿真波形； 3.选择实验电路进行验证, 由发光管指示显示结果。 -. The use of schematic and text input method input method to achieve full subtracter, hierarchical design, the bottom of t
butterfly1
- FFT 蝶形处理器的VHDL代码，由一个加法器，一个减法器和一个实例化为组件的旋转因子乘法器ccmul组成-FFT butterfly processor VHDL code by an adder, a subtracter, and an instance of the component into the composition of the rotation factor multiplier ccmul
quanjieqi
- 基于EDA开发系统箱上实现2位全减器的VHDL编程语言，附带波形仿真。-EDA development system based on the realization of two boxes full subtracter in VHDL programming language, with wave simulation.
LIBRARY-IEEE
- 底层文件2：h_subber.VHD实现一位半减器 顶层文件：f_subber.VHD实现一位全减器 -The underlying file 2: h_subber.VHD-to achieve a half- Top-level file: f_subber.VHD the realization of a full subtracter
Four-adder-of-subtracter
- 在max+plus II 的环境下设计4位全加器数字电路 使用vhdl语言，进行设计数字电路的RTL级电路 -Four full adder digital circuit design environment, max+ plus II RTL-level circuit, digital circuit design using vhdl language
11
- HSPICE 全加全减器设计 带波形仿真文件 超大规模集成电路设计-HSPICE full adder full subtracter design with VLSI design of the simulation waveform files
fVerrilog_Devr
- 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器，乘法器，多路选择器，二进制转BBCD码，加法器，减法器，简简单易懂状态机，四位比较器，7段数码管，i2c总线，lcd液晶LCD显示出来，拨码开关，串口，蜂鸣器，矩阵键盘，跑马灯，交通灯，数字时钟 可直接使用。 -Friends, I Jawen. See previous upload a
binary_adder_subtractor
- binary adder / subtracter in vhdl
v15-23
- paper related to adder/subtracter design using VHDL
FinalDesign
- 实现逻辑门电路的绘制以及运算。并且实现了加法器、减法器、乘法器、比较器等运算-Implementation of logic gate drawing and operation. And implement the adder, subtracter, multiplier, comparator and other operations
fdiv
- 用Quarters ii实现对减法器的仿真-In the Quarters ii realize the simulation of the subtracter
test8
- xilinx工程文件，test8.v是源代码，实现了逐位进位的加法器、减法器，和逻辑运算功能。运行通过，仿真成功。-Xilinx engineering documents, test8. V is the source code, to achieve the cascaded carry adder, subtracter, and logical operations function. Running through, the