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vh2sc
- 将VHDL转换为C的软件 将VHDL转换为C的软件-VH2SC is a free basic VHDL to SystemC converter. The converter handles a small subset of Synthesisable VHDL 87/93 language constructs. The current version translates all VHDL IEEE types to sc_
modu
- this the verilog code that performs the modulus function ... most importantly it is synthesisable... uses the repeated sub algorithm-this is the verilog code that performs the modulus function ... most importantly it is
LIP1611CORE_AES128_SEC_UWB
- AES 128 Synthesisable RTL code
LIP2301CORE_Synthesisable-RAM
- Verilog Synthesisable RAM source code
rom_verilog
- verilog 源代码，非常简单的一种ROM的可综合的写法，适合新手学习之用。-verilog source code，simply implementation of ROM with synthesisable coding-sytle， special for the beginners.
sram_verilog
- verilog 源代码，非常简单的一种SRAM的可综合的写法，适合新手学习之用。-verilog source code，simply implementation of SRAM with synthesisable coding-sytle， special for the beginners.
Verilog_primer_V1.1
- Verilog HDL 语言的编码规范。详细介绍了verilog HDL编码的注意事项和基本规范。分为可综合部分，仿真专用部分以及nc-verilog仿真环境的建立。-Descr iption of Verilog HDL coding. containing synthesisable language, simulationable language and how to construct a proper environment
grlib-netlists-1.1.0.tar
- leon for 3 fpu. The LEON3 is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable, and particularly suitable for system-on-a-chip (SOC) designs.
lpddr_verilog_model
- 美光 ddr sdram 仿真模型， 不可综合，用在测试平台模仿ddr sdram的功能。verilog语言编写。-Micron MOBILE DDR SDRAM simulation model. not synthesisable, used in tesetbench to emulation the function of ddr sdram. written in verilog
vhdl
- code for fft non synthesisable in xilinx ise
vhdl
- Modeling a synthesisable embedded microcontroller