搜索资源列表
ISP1362_IF
- ＡＬＴＥＲＡ上ＤＥ２平台的ＵＳＢ（ＩＳＰ１３６２）模块的底层Ｖｅｒｉｌｏｇ描述。-Altera DE2 platform on the USB (ISP1362) module bottom Verilo g descr iption.
Verilog-Semantics
- Synthesizable Verilo---syntax and semantics一本很好的关于verilog可综合设计的参考书-Synthesizable Verilo --- syntax and semantics a good Verilog synthesis of the reference design
YCrCb2RGB
- 用verilo编写的RGB编码，而且加入了流水线
Verilog-Semantics
- Synthesizable Verilo---syntax and semantics一本很好的关于verilog可综合设计的参考书-Synthesizable Verilo--- syntax and semantics a good Verilog synthesis of the reference design
ISP1362_IF
- ＡＬＴＥＲＡ上ＤＥ２平台的ＵＳＢ（ＩＳＰ１３６２）模块的底层Ｖｅｒｉｌｏｇ描述。-Altera DE2 platform on the USB (ISP1362) module bottom Verilo g descr iption.
gal
- 用于编可编辑芯片用,如gal16v18芯片等,有几个文件, 内有说明等!-Series can be used to edit the chips used, such as chips gal16v18, there are several documents, there are descr iptions!
uart_verilog
- this is a sample about UART transmission,it s default installation is D:\RedLogic\RCII_samples, and the software environment is quatrusII 5.0,it is usefull for studying UART.-this is a sample about UART transmission, it
I2C_HDL
- I2C bus HDL source and testbench
8080
- EPM1270和单片机的8080通讯接口，适合单片机与CPLD之间的高速通讯，verilog语言，QuartusII环境-EPM1270 and 8080 MCU communication interface for MCU and CPLD high-speed communication between, verilog language, QuartusII environment
YCrCb2RGB
- 用verilo编写的RGB编码，而且加入了流水线-Verilo prepared using RGB encoding, and joined the assembly line
crc_verilog
- HDLC控制协议中CRC校验码算法代码，为CRC16，Verilog语言-HDLC Control Protocol Code in the CRC checksum algorithm code for CRC16, Verilog language
PLD_SRAM
- PLD自增读写SRAM,有好的参照作用，希望大家指点和帮助。-PLD by reading and writing since the SRAM, has reference to the role of good, I hope everyone pointing and help.
SPI
- Verilog SPI 源码（来自网络）-Verilog SPI
counter1
- 带复位和时钟使能的十进制计数器 verilo 描述-With reset and clock enable verilo descr iption of the decimal counter
fivevhdl
- 5中cpu的程序，包含arm4，arm6，arm7等程序，的verilog实现-5 cpu procedures, including arm4, arm6, arm7 and other procedures, the verilog implementation
AD7705
- Verilog AD7705代码 对AD7705实时进行控制-Verilog AD7705 AD7705 real-time control code
Verilo
- 这是一个关于hdl的电子书，里面有比较详细的介绍，外文翻译版本-This is a hdl of e-books, which have a more detailed descr iption, foreign language translation
lcdtest
- Verilo LCD controller
AMBA-Bus_Verilog_Model
- 该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB
i2c
- I2C接口程序，整个工程文件，文人已仿真，下载，在ＦＰＧＡ上测试成功 verilo语言-I2C interface programme,the whole project file,I have simulated and tested in FPGA successfully .verilog language.