搜索资源列表
LAB5
- 七人表决器 七个按键,若按下个数多于三个,表示通过,LED点亮-Seven voting machines seven keys, press the number if more than three, said that through, LED lights
biaojueqi
- 七人表决器 当同意人数大于等于4时,投票通过。-Seven voting machines when the agreed number of greater than or equal 4, vote.
vhdlcoder
- 本文件夹包含了16个VHDL 编程实例,仅供读者编程时学习参考。 一、四位可预置75MHz -BCD码(加/减)计数显示器(ADD-SUB)。 二、指示灯循环显示器(LED-CIRCLE) 三、七人表决器vote7 四、格雷码变换器graytobin 五、1位BCD码加法器bcdadder 六、四位全加器adder4 七、英语字母显示电路 alpher 八、74LS160计数器74ls160
vote
- 此程序是七人表决器,代码中运用了case和IF这两种语句,可凭个人自由选用!-This program is a vote of seven, code in use of the case and the two IF statements, present their selection of individual freedom!
vote
- 当表决器的七个输入变量中有4个以上(含4个)为“1”时,则表决器输出为“1”;否则为“0”。分析七人表决器全加结果CBA(从高位到低位)中的八种情况:000-111,输出为“1”的量为100-111, 根据这种真值表用卡诺图化简可得出最简逻辑表达示为OUT=C,即全加结果最高位决定了结果。-failed to translate
qirenbiaojueqi
- 七人表决器,模拟评委表决,选择或者淘汰选手,大家可以看一下,能看懂的话可以修改人数哦。-Seven voting machines, analog judges vote choice or out of players, we can look at, to understand, then you can modify the number of oh.
vote7_plus
- 七人表决器完整工程项目,VHDL语言编写,Maxplus2环境,内有仿真图,实验可用-Seven voting integrity project, VHDL language, Maxplus2 environment, there are simulation diagram, experimental available ~ ~
FPGA
- 组合逻辑电路设计(编码器、译码器),时序电路设计(增计数器),图形设计输入实验 七人表决器设计-Combinational logic circuit (encoder, decoder), sequential circuit design (by counter), graphic design input experimental design of seven voting
VHDL
- 七人表决器,可以用于七人表决,很实用,很好,-Seven voting machines, you can vote for seven people, very practical, very good,
qrbjq
- 用FPGAS实现七人表决器,内含数码管显示。输入为七个开关,输出为数码管显示表决通过的人数,并用一个led灯显示表决结果(输入同意大于等于4灯亮否则灭,同时数码管显示同意的人数)。-FPGAS realize with seven people BiaoJueQi, contains the digital pipe display. Input for seven switch, output for digital pipe dis
7_ren_biao_jue_qi
- 用vhdl,设计的一个七人表决器,当赞成人数大于等于四时显示表决通过,同时分别将投票中赞成的人数和反对的人数在数码管上显示出来-VHDL design of a seven-vote in favor of the number of greater than or equal to four o' clock, the vote at the same time, respectively, displayed the numb
yy
- 七人表决器当选举人大于或等于4时为通过,绿灯亮;反之不通过时,黄灯亮。描述时,只须检查每一个输入的状态(通过为“1”,不通过为“0”),并将这些状态值相加,判断状态值和即可选择输出。-Seven voting machines when voters is greater than or equal to 4 through the green light the other hand does not pass, the yello
bjq7
- 七人表决器,7个人中至少4个人表示同意才回选择通过-Seven voting
VHDL-design-seven-people-voting
- 1、 熟悉VHDL的编程。 2、 熟悉七人表决器的工作原理。 3、 进一步了解实验系统的硬件结构。 -1, familiar with VHDL programming. 2, familiar with the seven voting machine works. 3, to further understand the experimental system hardware architecture.
Seven-voting-machines
- 用verilog编写的七人表决器代码·可以实现七人表决超过四人就通过的功能-Written in verilog seven voting machine code can be achieved seven people to vote on the adoption of more than four functions
Example18
- 七人表决器,可以实现7个人表决的小程序,计算表决同意人数,根据人数数码管显示表决通过人数-voting for seven people,7 people can vote applet
project9
- 七人表决器,利用全加器设计。当有四人或四人以上表决同意,实验箱上的指示灯亮-Seven people voting, the use of full adder design. When there are four or more than four agreed to vote on the bright lights test box
EDA
- EDA小程序,用VHDL语言设计七人表决器,四位加法器。-EDA small program design using VHDL seven people voting, four adder.
7renbiaojueqi
- FPGA开发实例 之 用VHDL设计七人表决器-The FPGA development instance of the design with VHDL voter of seven people
Arbiter-VHDL-based-design
- 1、熟悉VHDL的编程。 2、熟悉七人表决器的工作原理。 3、进一步了解实验系统的硬件结构。 -Arbiter VHDL-based design