搜索资源列表
add_full_n
- 该程序实现的是n位全加器，首先用与非门实现一位全家器，最后实现n位的全加器。-the program is to achieve the n-bit full adder, first using the door with non-realization of a family- and finally realize the full n-bit adder.
verilog实例
- 一些很实用的verilog源程序，是初学者的好棒手，希望能给需要的人一点帮助，请支持一下。-some very practical Verilog source is the beginners excellent hands, in hopes of giving those who need a bit of help, please support what.
quanjiaqi
- 全加器的详细设计思路和用VHDL语言编写的详细源代码-increase for the whole of the detailed design ideas and the use of VHDL for preparing a detailed source code
399
- 用VHDL编写的8位全加器,数字分频器等程序-VHDL prepared by the eight All-Canadian, digital dividers procedures
5-2-2Syn
- synplify环境下 实现 全加器 功能-synplify environment to achieve full functionality increases
128bitminus
- 128乘法模拟器 c M位乘N位不带符号整数的阵列乘法中加法---移位操作的被加数矩阵.每一部分乘积项ab叫做一个被加数.m*n个被加数可以用m*n个”与门”并行的产生. 以5位乘5位不带符号的阵列乘法器(m=n=5)为例(如下图): FA为一位全加器,FA的斜线方向为进位输出,竖线方向为和输出,而所有被加数项的排列和正常的A*B=P乘法过程中的被加数矩阵相同.图中用矩形围成的阵列中最后一行构成一个行波进位加法器,其时
fulleradder
- 本程序以Modelsim为开发平台，采用VHDL为开发语言，实现了简单的全加器．适合初学Modelsim的同行-Modelsim the procedures for the development of a platform for the development of VHDL language, achieving a simple full adder. Suitable for a novice counterparts Mo
Afixed-pointbasecomplementdivider
- 由寄存器,全加器,移位寄存器,计数器,触发器和门电路构成补码一位除法器,将开关设定的补码形式出现的除数,被除数存入相应寄存器中.能用单脉冲按步演示运算全过程.-From the register, full adder, shift register, counters, flip-flops and gates constitute a complement divider will switch set in the form o
h_adder
- 本文件包是在MAX+plus II 软件环境下实现全加器的逻辑功能-This document packet was MAX+ Plus II software environment to achieve full adder logic function
add_1p
- 2级流水线实现的8位全加器的VHDL代码，适用于altera系列的FPGA/CPLD-Realize two lines of eight full adder of the VHDL code, applicable to altera series of FPGA/CPLD
add_2p
- 2级流水线，使用4元件实现的22位全加器的VHDL语言实现，适用于altera的FPGA-2 lines, use the 4 components realize the full adder 22 of the VHDL language, applicable to altera the FPGA
add_3p
- 3级流水线，含4元件的22位全加器的VHDL语言实现，适用于altera系列的FPGA-3-stage pipeline, with 4 components of 22 full adder realize the VHDL language, applicable to altera Series FPGA
add_ff8cin
- 触发器实现的，8位全加器的VHDL语言实现，适用于altera系列的FPGA-Flip-flop to achieve, eight full adder realize the VHDL language, applicable to altera series FPGA
quanjia
- 全加器，使用宏功能模块，并附有波形仿真图-Full adder, the use of macro functional blocks, together with simulation waveform diagram
zxfg
- 四位全加器语言描述是以文本方式上传的，呵呵，希望大家有帮助-Four full-adder based on the text of the language to describe the way to upload, huh, huh, hope that we have to help
fulladder
- 全加器,有半加器和或门组成.元件例化语句.-Full adder, half adder and OR gate components. Components of sentence cases.
verilog5
- verilog语言中 testbencch编写-仿真工具综合工具使用-全加器实例讲解-Verilog language testbencch preparation- the use of simulation tools integrated tools- examples of full adder on the
VHDL-XILINX-EXAMPLE26
- [VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][6--8位并入串出寄存器][7--内部三态总线][8--含清零和同步时钟使能的4位加法计数器][9--数控分频器][10--4位十进制频率计][11--译码扫描显示电路][12--用状态机实现序列检测器的设计][13--用状态机对ADC08
f_adder
- 用VHDL语言采用串行方法实现用1位全加器实现4位全加器-Using VHDL language using the serial method of using a full adder realize four full adder
1002016p_Sa
- 设计一个两位全加器，并用发光二极管显示结果。全加器的三个输入（二个数字输入，一个进位输入）用实验箱中W1,SW2,SW3控制，二个输出用发光管LED1,LED2显示。整个设计采用层次设计方法，顶层文件采用原理图输入法。整个电路设计思路分三部分： 1半加器电路设计； 2.全加器电路设计，是在半加器的基础上设计的； 3.数据输入，输出电路设计。 -The design of a two full-adder, and the