搜索资源列表
Calculator
- 采用FPGA编写代码,包含了3-8译码器,加法器,减法器,乘法器的功能。-The FPGA write code, including a 3-8 decoder, adder, subtractor, multiplier function.
Add_sub_struc
- 8位加减器,八位减法器与加法器,用过一个控制端可以自由变换,采用移位加法方式,用途广泛,利用减法位补码加法的理论实现。-8 addition and subtraction, eight subtractor and adder, used a control terminal can freely change the using Shift addition, a wide range of uses, the use of sub
addersubtractor
- 用verilog语言编写并通过综合验证的加法减法器的工程目录-the design and implementation of addersubtractor using verilog
Traffic-light-on-corssline-
- 本实验中主要应用了状态机以及减法器的设计原理。在状态连续变化的数字系统设计中,采用状态机的设计思想有利于提高设计效率,增加程序的可读性,减少错误的发生几率。同时,状态机的设计方法也是数字系统中一种最常用的设计方法。一般来说,标准状态机可以分为穆尔(Moore)机和米利(Mealy)机两种。在穆尔机中,其输出仅仅是当前状态值的函数,并且仅在时钟上升沿到来时才发生变化。米利机的输出则是当前状态值、当前输出值和当前输入值的函数。-In thi
designlab-final-2
- 用软件方式实现加法器、减法器、寄存器等硬件功能,可以自主连接。并有32位BLOCK抽象,与单个门进行连接-Using software to achieve the function of adder, subtractor, register and so on. You can connect wires between gates. Also there is a block demo mode which abstract th
fudian_sub
- 实现32位浮点减法器,具体结合加法器和乘法器来实现快速傅里叶变换。-use VHDL to finish the sub device.
fudian_mul
- 实现32位浮点减法器,具体结合加法器和乘法器来实现快速傅里叶变换。-use VHDL to finish the sub device.
Addition
- mfc界面的加法减法器,带注释,文件为vs2010工程,使用请重新编译-mfc interface adder subtractor, annotated, file vs2010 engineering, use please recompile
fVerrilog_Devr
- 朋友,我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的,现在就将她的Verilog源码也一并贡献给大家:8位优先编码器,乘法器,多路选择器,二进制转BBCD码,加法器,减法器,简简单易懂状态机,四位比较器,7段数码管,i2c总线,lcd液晶LCD显示出来,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟 可直接使用。 -Friends, I Jawen. See previous upload a
add_ded_module
- 使用Verilog语言编写的4位加减法器,经验证能在FPGA开发板上实现。-Verilog4 bit adder-subtractor.
FPGAVerilog_HDLjiaotongdeng
- verilog 语言实现交通灯的控制,利用减法器通过重置初始值实现
src
- n位二进制绝对值减法器,基于FPGA的硬件语言-n-bit binary absolute value subtraction, FPGA-based hardware language
VHDL_book2
- add4a:4位加法器的设计 add8a:8位加法器的设计 subtract:4位减法器的设计 addsub: 4位加法器/减法器的设计 shift4:移位寄存器的设计 mult4:乘法器设计 div8:除法器设计 alu4:算术逻辑单元ALU设计-add4a: 4-bit adder design add8a: 8 bit adder design subtract: 4-bit subtr
BCD_subtracter
- VHDL编写的7位BCD减法器,可实现带小数点减法运算。-VHDL, 7 BCD subtraction, which can be achieved with a decimal point subtraction.
jianfa_sub
- 基于FPGA的减法器的verilog程序源代码-FPGA-based subtractor verilog source code
jian
- 基于FPGA减法器,实现二进制减法功能,Altera为FPGA初学者详细介绍了FPGA基础知识以及怎样开始进行FPGA设计-FPGA-based subtractor achieve binary subtraction functions, Altera FPGA beginners as described in detail the basics of FPGA FPGA design and how to start
excess-3-code-adder-subtructer
- 余3码excess-3 code加法器和减法器,用vhdl实现-I 3 yards excess-3 code adder and subtractor using vhdl
FinalDesign
- 实现逻辑门电路的绘制以及运算。并且实现了加法器、减法器、乘法器、比较器等运算-Implementation of logic gate drawing and operation. And implement the adder, subtracter, multiplier, comparator and other operations
fdiv
- 用Quarters ii实现对减法器的仿真-In the Quarters ii realize the simulation of the subtracter
test8
- xilinx工程文件,test8.v是源代码,实现了逐位进位的加法器、减法器,和逻辑运算功能。运行通过,仿真成功。-Xilinx engineering documents, test8. V is the source code, to achieve the cascaded carry adder, subtracter, and logical operations function. Running through, the