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有时钟使能端的十进制计数器
- 有始终使能端的十进制计数器，经验证可以实现-have always enable side of the decimal counter, the experience can be achieved certification
十进制计数器和数字钟
- 此程序是两个简单十进制计数器和数字钟，不完备之处请指教，谢谢！-this procedure is a simple two decimal counter and digital clock, from incomplete please enlighten, thank you!
有时钟使能端的十进制计数器
- 有始终使能端的十进制计数器，经验证可以实现-have always enable side of the decimal counter, the experience can be achieved certification
十进制计数器和数字钟
- 此程序是两个简单十进制计数器和数字钟，不完备之处请指教，谢谢！-this procedure is a simple two decimal counter and digital clock, from incomplete please enlighten, thank you!
COUNT_10
- VHDL源代码.设计一个带有异步清0功能的十进制计数器。计数器时钟clk上升沿有效，清零端为clrn,进位输出为co。 -VHDL source code. Asynchronous design with a 0-counter function of the metric system. Counter clock clk ascending effective end to reset clrn, rounding outpu
vhdl_clock
- VHDL实现数字时钟，利用数码管和CPLD 设计的计数器实现一个数字时钟，可以显示小时，分钟，秒。程序主要要靠考虑十进制和六十进制计数器的编写。 以上实验的程序都在源代码中有详细的注释-VHDL digital clock, the use of digital control and CPLD design to achieve a number of counter clock, show hours, minutes and
Module=99ReversibilityCounter
- 设计功能及要求 设计M=99的十进制加/减可逆计数器 （1）接通电源时电路能自启动； （2）手动分别实现加、减计数和自动实现加减可逆计数； （3）用数码管显示计数数值。 (4）给定元件：74LS192、74LS00、74LS76、74LS48及LED。-Design features and requirements of the design of the metric M = 99 plus/minus
COUNT10
- 一个十进制计数器的vhdl程序，大家可以参考，已经经过编译了-A decimal counter VHDL process, everyone can refer to, has been compiled
1002016p_Sa_5
- 用ＶＨＤＬ语言实现８位十进制计数器的设计，计数结果用实验板上8个数码管显示-VHDL language with eight decimal realize the design of counters, counting the results of experiments on-board with 8 digital tube display
seg73
- 递增方式在4位数码管上向上计数显示从0000-0001->0002……..9999….0000….0001…. -- 利用CPLD设计了一个4位十进制计数器，并用数码管显示当前计数值-Incremental approach in the four counts upward digital tube display from 0000-0001-
pinluji
- 四位十进制频率计设计 包含测频控制器（TESTCTL），4位锁存器(REG4B)，十进制计数器（CNT10）的原程序(vhd)，波形文件(wmf ),包装后的元件(bsf)。顶层原理图文件（Block1.bdf）和波形。 -Four decimal frequency meter measuring frequency controller design includes (TESTCTL), 4 bit latch (REG4
count10
- 用vhdl编写的十进制计数器，内部说明详细。-Prepared using VHDL decimal counter, the internal descr iption in detail.
t1
- 带清零和重置功能的十进制计数器，可以用LED灯显示结果-Cleared and reset with the decimal counter, can use LED lights display the results
bcd
- EDA 十进制计数器、BCD VHDL源代码-EDA decimal counter VHDL source code
jishuqi8421
- 用VHDL语言实现8421码的十进制计数器，状态变化0000->0001->0010->0011->0100->0101->0110->0111->1000->0000.循环往复。 -VHDL language with 8421 yards of the decimal counter, a state of change 0000-> 0001-> 0010-&g
CNT10-START
- 十进制计数器的设计的源代码 verilog语言 -conter10
counter6_t10jia
- 这是一个用VHDL编写的十进制计数器程序通过编译-This is a work written in decimal counter VHDL
count
- 用VHDL实现一个四位十进制计数器来进行计数，并且仿真通过-To use VHDL to achieve a 4 decimal counter to count, and the simulation through the
jishuqi
- 计数器，十进制计数器，完成计数的功能，满10进1-Counter, the decimal counter, the completion of counting functions, into a full 10
counter10
- vhdl编写的十进制计数器，名字叫count10，已配好引脚(VHDL's decimal counter, named count10, has been matched with a pin)