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ppt
- Verilog数字系统设计教程（夏宇闻）例题源程序 ppt-Verilog digital system design course (XiaYuwen) sample source program PPT
Verilog-xiayuwen-text
- Verilog数字系统设计教程（夏宇闻）例题源程序-Verilog digital system design course (XiaYuwen) sample source program
Verilog
- 夏宇闻 Verilog数字系统设计教程 源码,包括书中的全部内容，非常实用-Xia Yu Wen Verilog digital system design tutorial source code, including the entire contents of the book is very practical
Xia-Yu-Wen-Verilog-classic-tutorial
- 《夏宇闻-Verilog经典教程.pdf》夏宇闻教授的经典Verilog讲解！-"Xia Yu Wen-Verilog classic tutorial. Pdf" Xia Yu Wen Professor classic Verilog explain!
VerilogHDL
- 非常好的夏宇闻的veilogHDL语言学习资料，非常难得的。-Very good the xiayuwen of verilog HDL of language learning materials, and very rare.
xiayuwen_Verilog-HDL
- 夏宇闻版的Verilog习题源程序，带有测试模块，和仿真波形。-examples of Xia Yuwen
Verilog
- 夏宇闻fpga经典教程，verilog设计教程，值得一看-Xia Yuwen the fpga classic tutorial, worth a visit
Verilog
- 夏宇闻-Verilog经典教程，学习Verilog入门必看-Xia Yu Wen-Verilog classic guide to learn Verilog entry must see
my_IIC_Verilog
- 参考夏宇闻书中用verilog实现的i2c接口，有详细解释-Reference Yu Xia Wen book verilog i2c interface to achieve a detailed explanation
risc_cpu-OK
- 夏宇闻 verilog数字系统设计教程源码 第二版，实现了简单的RISC CPU。印刷版有误，已改正。- A simple RISC CPU Verilog HDL source code. Work well.
Verilog
- Verilog教程-夏宇闻 讲的比较全面 适合初学者-Verilog tutorial- Xia Wen speak more comprehensive for beginners
Verilog-classic-tutorial
- verilog经典教程 夏宇闻老先生翻译-the old gentleman translation of the verilog Classic teach Cheng Xiayu smell
Verilog-design-
- 数字逻辑基础与Verilog设计 夏宇闻版 书籍附的代码和附录文档。-The basis of digital logic with Verilog design Xia Yu Wen-print books attached code and Appendix document.
digital-logic-design-(FPGA)-based
- 夏宇闻老师的经典数字逻辑设计（基于FPGA）-Xia Wen teacher classic digital logic design (FPGA)-based
Verilog-HDL-PPT
- Verilog HDL 经典教程夏宇闻老师主讲PPT-The Verilog HDL Classic teach Chengxia Yu Wen speaker teachers PPT
Verilog-HDL-Digital-Design
- Verilog HDL 数字设计与综合 夏宇闻-Verilog HDL Digital Design and Xia Wen
IIC
- 夏宇闻<Verilog数字系统设计教程>源代码，已经可综合和实现，可以用Modelsim编译-Xia Wen <Verilog数字系统设计教程> Source code, has been integrated and implemented can be compiled using Modelsim
risc_cpu
- RISC_cpu，包括所有的模块与测试文件。是夏宇闻第二版书中的错误均已改正，运行正确后上传，请放心使用。-RISC_cpu, including all modules and test files. Xia Wen error of the second edition of the book have been correct, to run correctly upload, please feel free to use.
From-Arithmetic-to-Hardware-Logic
- 夏宇闻著作：从算法设计到硬线逻辑的实现.DOC Verilog HDL的基本算法及实现-From Arithmetic to Hardware Logic. Verilog HDL
I2C_EEPROM
- 1. 本测试是夏宇闻 verilog数字系统设计教程，中的例程。 2. 编译环境Quartusii 3. 仿真环境Modelsim se 6.5d 4. 可综合部分已经经过quartus 验证正确 5. 仿真部分通过将I2C模块与一个EEPROM模型组合，通过时序仿真-EEPROM_I2C Verilog