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序列检测器
- 不仅有源码，还有仿真波形图，看看会有帮助的
lxh_xulijianceqi
- 这是1个序列检测器,可以重复检测序列,在通信方面用的较多-This is a sequence detector, can detect repeat sequence, in communications with the more
s_machine
- right.vhd 序列发生器 s_machine.vhd 序列检测器 波形图.doc 程序运行波形-right.vhd s_machine.vhd sequence generator waveform sequence detector map. doc procedures Waveform
xuliejiance
- 《序列检测器》绝对好用的EDA实验程序,已经通过测试！VHDL语言编写-"Sequence Detector" absolutely good for EDA experimental procedure, he has passed the test! VHDL language
expt81_schk
- 基于fpga和sopc的用VHDL语言编写的EDA序列检测器-FPGA and SOPC based on the use of VHDL language EDA sequence detector
xljcq
- 用vhdl语言实现序列检测器的设计 这是学习VHDL语言的经典例子-Using VHDL language sequence detector design VHDL language learning this is a classic example of
XLJC
- 用状态机实现串行序列检测器的设计 若检测到串行序列11010则输出为1 否则输出为0 并对其进行仿真和硬件测试-State machine used to achieve serial sequence detector designed to detect if the serial sequence 11010 output to 1 otherwise the output is 0 and its simulation and
xu
- 序列发生器,产生一个8位序列号,序列码可自定义修改,还有一个序列检测器 -Sequence generator, producing an 8-bit serial number, serial code can be customized to amend, there is a sequence detector
xuliejiancesheji
- 用状态机实现一序列检测器，即检测到串行码{1110010}后，检测器输出1，否则输出0； -State machine used to achieve one sequence detector, which detects the serial code (1110010), the detector output 1, otherwise output 0
111
- 使用JK触发器设计111序列检测器，当检测到输入为111时输出为1，否则为0-JK flip-flop design using the sequence detector 111, when input 111 is detected when the output 1, otherwise 0
Sequencedetector
- 用VHDL语言实现的序列检测器 （以1010111为例）-Sequence detector (for example 1010111)
Sequence-detector-design
- 序列检测器设计的思路大多都是用FSM来实现的,此思路是通过移位寄存器来实现序列检测-Sequence detector design ideas are often used to achieve the FSM, the idea is to achieve through the shift register sequence detection
Sequencedetector
- 序列检测器可用来检测一组或多组由二进制码组成的脉冲序列信号，这在数字通信领域有广泛的应用。当检测器连续收到一组串行二进制码后，若这组码与检测器中预制的码相同，输出为A，否则输出为B。序列检测I/O口的设计如下：设Din是串行数据输入端，clk是工作时钟，clr是复位信号，D是8位待检测预置数，QQ是检测结果输出端。-Sequence detector can be used to detect one or more sets cons
EDA3add
- 序列信号发生器与检测器设计：用状态机设计实现串行序列检测器的设计，先设计（可用原理图输入法）序列信号发生器产生序列：0111010011011010；再设计检测器，若检测到串行序列11010则输出为“1”，否则输出为“0”，并对其进行仿真和硬件测试。-Sequence signal generator and detector design: The Design and Implementation of a serial seque
VHDL
- 序列检测器设计VHDL源程序 任意输入串行数据串-VHDL source code sequence detector design arbitrary string of serial data input
8_1
- 一个具有置位、复位、左移和右移功能的八位移位寄存器/“01011010”序列检测器。移位寄存器电路端口为：异步清零输入端口rst，输入时钟clk，置数判断输入端口load，移位类型判断输入端口m，数据输入端口data[7:0]，输出端口q[7:0]。序列检测器电路端口为：异步清零输入端口rst，输入时钟clk，串行数据输入端口d，输出标志端口s。(A eight bit shift register / 01011010 sequenc
序列检测器
- 本例子为一个序列检测器的程序，序列为：110010010000100101００，检测的序列为10010(This example is a sequence detector procedure, the sequence is: 11001001000010010100, the detection sequence is 10010)
序列检测器设计
- 序列检测程序，检测数列中的程序。希望对大家有帮助，版权所有，只可以作为参考(i do not speak english this is a number process .sjkjskjd znbjsahh isa siu oa u uasidui yauyd adyius i sauyi i aidus)
110序列检测器
- 110的序列检测器，添加了使能端检查其正确性(The sequence detector of 110 adds the enable end to check its correctness.)
6bit序列检测器
- 1、用数码管显示被检测的连续数字序列，MSB在前； 2、当输入的数字序列连续六个值等于一组串行码（如00011101）时输出高电平并报警显示，同时用两位数码管显示出现的次数。 3、串行码的值可设定(6bit sequence detector)