搜索资源列表
Adnence_add8
- VHDL实现的超前进位加法器-the VHDL-ahead Adder
ADD_SUB
- 11,13,16位超前进位加法器的Verilog HDL源代码。-11,13,16-CLA for the Verilog HDL source code.
booth_mul
- 一种可以完成16位有符号／无符号二进制数乘法的乘法器。该乘法器采用了改进的Booth算法，简化了部分积的符号扩展，采用Wallace树和超前进位加法器来进一步提高电路的运算速度。本乘法器可以作为嵌入式CPU内核的乘法单元，整个设计用VHDL语言实现。-a 16 to be completed with symbols/unsigned multiplication of the number of binary multipliers.
cla_vhd
- 超前进位加法器的例子,包括源码和测试文件,压缩包,无密码.-CLA of examples, including source code and test documents, compressed, without a password.
adder_ahead8bit
- 本文件提供了用verilog HDL语言实现的8位超前进位加法器,充分说明了超前进位加法器和普通加法器之间的区别.-using verilog HDL achieve the eight-ahead adder, fully demonstrates the CLA for ordinary Adder and the distinction between.
LAC_adder16
- 十六位超前进位加法器，Verilog HDL-16-ahead adder, Verilog HDL
CLA8
- 一个超前进位加法器的Verilog实现，内含测试文件，可以综合，非常有参考价值-A CLA of Verilog realize that contains the test documents, can be integrated and very useful
ahead_adder
- 用Verilog语言实现了一个8bit的超前进位加法器，其中包括测试文件。-Verilog language using an 8bit realize the CLA, including the test file.
CLA
- 超前进位加法器得VHDL实现小点资料代码-CLA was a small point of information VHDL code
adder
- 8位超前进位加法器 就是使各位的进位直接由加数和被加数来决定，而不需要依赖低位进位-8-bit CLA is to make your binary direct summand by summand and to decide, rather than to rely on low binary
add2
- 两个4bit超前进位加法器实现8bit加法器-Two 4bit CLA realize 8bit adder
trueif
- 一个超前进位加法器（及其testbench) .v文件-A CLA (and its testbench). V file
adder_32
- 超前进位加法器是通常数字设计所必备的，本程序为32位超前进位加法器-CLA is usually necessary for digital design, the procedure for 32-bit CLA
16bitCLA
- 基于Verilog HDL的16位超前进位加法器 分为3个功能子模块-Verilog HDL-based 16-bit CLA is divided into three functional sub-modules
adder17
- 实现17位加法，利用一个16位超前进位加法器和一个一位全加器构成的一个有进位输入和进位输出的17加法器，并且16位加法器利用的使四位超前进位加法器构成。它在booth乘法器设计中经常用到。可以使初学者对模块的调用了解更加透彻。-Adder 17 to achieve the use of a 16-bit CLA, and a one-bit full adder composed of a binary input and binar
HG_chufaqi_clajiafaqi
- VHDL基-16位的无符号除法器，超前进位加法器可改位数。-VHDL-based-16 bit unsigned divider, CLA can be the median.
adder
- 本设计是做了一个32位超前进位加法器，能够快速计算-This design is made of a 32-bit lookahead adder, to quickly calculate
超前进位加法器
- 8*8超前进位加法器，Verilog初学教程(file name is adder.v adder 8*8 bit)
4Bit超前进位加法器门级电路设计与仿真
- 用门级网表的方法对4Bit超前进位加法器门级电路连接关系用verilog语言进行描述(The connection relation of the gate level circuit of 4Bit carry adder is described in Verilog language with the method of gate level netlist)
16位超前进位加法器
- 16位超前进位加法器的报告，报告里面含有主代码测试代码仿真结果(16 bit forward adder)