用Verilog语言实现的5位频率计设计，为实现功能验证，测频信号是由内部时钟源分频得到，为25KHZ，数据输出为串行输出。使用的硬件资源是altera公司的EPM7218，晶振为40MHZ。-Verilog language used to achieve the five frequency meter design, to achieve functional verification, signal frequency measurement by the internal clock