VHDL编写。在CPLK开发板上设计的数字钟的去抖动电路。该模块相对独立，是学习去抖动的好资料。该模块跟我其它的8个模块配套构成一个数字钟。-Programmed with VHDL.A debouncing circuit which is part of a digital clock designed on a CPLD development board.The module is independent from others and is useful for learning de