采用Verilog编写的存储器，使用lpm_ram_dq模拟主存。主要内容为实现了存储器的奇偶分体，使得该存储器可以进行字或字节的读写操作。-Written by Verilog memory, use lpm_ram_dq simulated main memory. The main content of the memory parity split making the memory word or byte read and write operations.