带有置位和清零端的边沿D触发器的设计与实现.带有置位和清零端的边沿D触发器的逻辑图，本实验中用Verilog语句来描述。-Design and implementation of an edge D flip-flop with set and reset end. Logic diagrams with edge D flip-flop with set and reset the end of the Verilog statement, used in this experiment to