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Lab13_mod5cnt
- 模-5计数器就是从0到4重复计数。也就是说,它一共要经历5个状态,输出从000变到100然后再回到000。本实验中用Verilog语句来描述。-Module-5 counter is from 0 to 4 repeat count. That is to say, it has to experience 5 state, the output from 000 to 100 and then to 000. Using the Verilog statement in this experi