Synplify Pro综合流程序仿真，注：本范例同时提供Verilog和VHDL两种语言版本，请读者根据习惯选用不同的源代码进行操作。-Synplify Pro comprehensive process simulation (note: this example provides two Verilog and VHDL language version at the same time, please choose the different readers according to t