FPGA设计中，实现基准时钟的分频模块，该模块是将外围电路中所提供的50MHZ将其分频，对时钟模块作用后产生一秒一秒的时钟信号，另外对显示模块的计数器提供时钟实现显示模块的扫描功能。(The design of FPGA, the reference clock frequency module, this module is provided in the peripheral circuit of the 50MHZ frequency, the clock module generates