一个简单的Modular Design设计,源代码，分别用Verilog和VHDL两种语言描述，本设计顶层模块由3个子模块组成.-Modular Design of a simple design, source code, respectively, with Verilog and VHDL descr iption of the two languages, the design of top-level module from the 3 sub-module.