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MPX CPU
- Open source implementation of MPX CPU (mips compatible) in Verilog
S1 CPU core
- S1 Core (codename Sirocco) is an open source hardware microprocessor design developed by Simply RISC. Based on Sun Microsystems' UltraSPARC T1, the S1 Core is licensed under the GNU General Public License, which is the license Sun chose for the OpenS
Multirate Digital Signal Processing
- Multirate Digital Signal Processing book from Prentice Hall, 1983
DSP implementation in FPGAs
- Digital Signal Processing in Field Programmable Gate Arrays
Flexpret CPU core
- Flexpret is RISCv implementation core hardware multithreaded