文件名称:6_seg_cpu
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我写的6段流水线cpu，供大家参考。里面包括了alu memory topcpu等模块-I wrote a six-stage pipeline CPU, for your reference
相关搜索： 流水线cpu
(系统自动生成,下载前可以参看下载内容)
下载文件列表
leg_source
..........\inst_code.txt
..........\leg.v
..........\leg_dcache.v
..........\leg_define.v
..........\leg_dpram_syn.v
..........\leg_icache.v
..........\leg_mem_arbitor.v
..........\leg_mult.v
..........\leg_rf.v
..........\leg_shifter.v
..........\leg_soc.v
..........\leg_soc_tb.v
..........\leg_tb.v
..........\stack_test.cr.mti
..........\stack_test.mpf
..........\trace.txt
..........\work
..........\....\leg
..........\....\...\verilog.asm
..........\....\...\_primary.dat
..........\....\...\_primary.vhd
..........\....\leg_dcache
..........\....\..........\verilog.asm
..........\....\..........\_primary.dat
..........\....\..........\_primary.vhd
..........\....\leg_dpram_syn
..........\....\.............\verilog.asm
..........\....\.............\_primary.dat
..........\....\.............\_primary.vhd
..........\....\leg_icache
..........\....\..........\verilog.asm
..........\....\..........\_primary.dat
..........\....\..........\_primary.vhd
..........\....\leg_mem
..........\....\.......\verilog.asm
..........\....\.......\_primary.dat
..........\....\.......\_primary.vhd
..........\....\leg_mult
..........\....\........\verilog.asm
..........\....\........\_primary.dat
..........\....\........\_primary.vhd
..........\....\leg_rf
..........\....\......\verilog.asm
..........\....\......\_primary.dat
..........\....\......\_primary.vhd
..........\....\leg_shifter
..........\....\...........\verilog.asm
..........\....\...........\_primary.dat
..........\....\...........\_primary.vhd
..........\....\leg_tb
..........\....\......\verilog.asm
..........\....\......\_primary.dat
..........\....\......\_primary.vhd
..........\....\_info
..........\Workbook of LEG.pdf
..........\inst_code.txt
..........\leg.v
..........\leg_dcache.v
..........\leg_define.v
..........\leg_dpram_syn.v
..........\leg_icache.v
..........\leg_mem_arbitor.v
..........\leg_mult.v
..........\leg_rf.v
..........\leg_shifter.v
..........\leg_soc.v
..........\leg_soc_tb.v
..........\leg_tb.v
..........\stack_test.cr.mti
..........\stack_test.mpf
..........\trace.txt
..........\work
..........\....\leg
..........\....\...\verilog.asm
..........\....\...\_primary.dat
..........\....\...\_primary.vhd
..........\....\leg_dcache
..........\....\..........\verilog.asm
..........\....\..........\_primary.dat
..........\....\..........\_primary.vhd
..........\....\leg_dpram_syn
..........\....\.............\verilog.asm
..........\....\.............\_primary.dat
..........\....\.............\_primary.vhd
..........\....\leg_icache
..........\....\..........\verilog.asm
..........\....\..........\_primary.dat
..........\....\..........\_primary.vhd
..........\....\leg_mem
..........\....\.......\verilog.asm
..........\....\.......\_primary.dat
..........\....\.......\_primary.vhd
..........\....\leg_mult
..........\....\........\verilog.asm
..........\....\........\_primary.dat
..........\....\........\_primary.vhd
..........\....\leg_rf
..........\....\......\verilog.asm
..........\....\......\_primary.dat
..........\....\......\_primary.vhd
..........\....\leg_shifter
..........\....\...........\verilog.asm
..........\....\...........\_primary.dat
..........\....\...........\_primary.vhd
..........\....\leg_tb
..........\....\......\verilog.asm
..........\....\......\_primary.dat
..........\....\......\_primary.vhd
..........\....\_info
..........\Workbook of LEG.pdf