搜索资源列表
TEA5767-PLL
- TEA5767-PLL收音机整套方案（汇编源码）-TEA5767 - PLL radio package (compiled source code)
DDS+PLL
- 基于FPGA的新的DDS+PLL时钟发生器-FPGA-based new DDS PLL clock generator
pll
- 关于锁相环的MATLAB的仿真程序，其中有详细的注释，希望它能能对你的能有所帮助-PLL on the MATLAB simulation program, including a detailed Notes hope it can be your right, can be helped
pll
- matlab在电力电子技术仿真中运用，包括PLL的具体仿真实现，一些滤波算法的实现，很有用
pll
- fpga中pll时钟实现的源代码，可实现倍频或分频
A.spur-free.fractional-N.pll
- A new PLL topology and a new simplified linear model are presented. The new fractional-N synthesizer presents no reference spurs and lowers the overall phase noise, thanks to the presence of a SampleJHold block. With a n
Matlab-based-simulation-PLL-design-
- 基于Matlab仿真的数字锁相环的设计进行了详细的分析和模拟，数字和模拟锁相环的论文-Matlab-based simulation of digital PLL design, a thesis on digital and analog phase-locked loop for a detailed analysis and simulation
pll
- C++ programm. Digital pll.
PLL
- PLL锁相环仿真文件，附带解释，完美实现(PLL phase locked loop simulation file, with explanation, perfect realization)
CD4046 PLL Test
- CD4046 PLL Test circuits
PLL
- Basics of PLL and its working clearly explained
2-PLL
- PLL of TI 5509 derived in code compser
DDSRF-PLL
- 本文论述了在控制的一个重要方面电网连接的电源转换器，即检测基波正序分量的电网电压不平衡和扭曲的条件下。明确地,提出了一种积极的基于一种新的序列检测器双同步坐标系的解耦锁相环（双dq–PLL），完全消除了检测误差传统的同步参考框架（SRF–锁相环PLL）。(This paper deals with an important aspect in the control of grid connected power converters,
ADF4351-V1.1(pll)
- PLL模块点频输出，可产生35Mhz~120Mhz稳定正弦信号(PLL point frequency output)
dsPIC33 PLL settings
- 这是Microsoft Office 的Exel样式的计算软件。用这软件来很容易算出dsPIC33F单片机的PLL频率。(This is calculating program for frequency setting of dsPIC33F PLL.)
pll
- 封装的matlab程序，实现数字锁相环的功能函数(Encapsulated matlab program to implement the function function of the digital PLL)
pll
- this is pll for verilog
PLL
- pll的matlab仿真模型，完整，可以使用(Matlab simulation model of PLL,Complete,can be used)
PLL
- 实现了lpc2103单片机的pll功能，通过查询方式与中断方式实现(The PLL function of LPC2103 single chip computer has been realized)
PLL
- 通过对输入时钟进行锁相环IP核配置，产生所需的时钟信号(By configuring the input clock PLL, the IP core generates the desired clock signal)