搜索资源列表
add_2x32_v1
- 2*32乘法器设计,只是部分Booth乘法器的设计,相关的后面部分将在需要时陆续上传。-design of an 2*32Multiplier
95637012Multiplier
- 一种可以完成16位有符号/无符号二进制数乘法的乘法器。该乘法器采用了改进的booth算法,简化了部分积的符号扩展,采用Wallace树和超前进位加法器来进一步提高电路的运算速度。本乘法器可以作为嵌入式CPU内核的乘法单元,整个设计用VHDL语言实现。- This file contains all the entity-architectures for a complete-- k-bit x k-bit Booth multipli
New-folder
- VHDL codes for booth , nco and some more
VHDL-test-codeBooth-multiplier
- VHDL实验代码:Booth乘法器,是一个基于VHDL语言开发的程序,非常的实用-VHDL test code: Booth multiplier, is a VHDL-based language development program, a very practical
multiplier
- 参数可配置的sequential 乘法器和booth 乘法器-verilog source code with configurable parameters for sequential multiplier and booth multiplier
booth_multiplier
- This source code makes 8 X 8 booth multiplier and it is coded in Velilog HDL.
booth_multiplier
- Booth Multiplier Radix-2
The-Booth-Tolls-for-Thee
- 细胞自动机的matlab代码,数学中国上下载的,供数学建模的参考。-Cellular automata matlab code, mathematics Chinese to download for reference, mathematical modeling.
booth_mult
- 布斯乘法器的verilog实现及仿真文件,使用modelsim仿真-booth mult s verilog and test
qiyeshopping
- 设计一个企业电子销售管理系统,该系统的用户分别是: 会员和系统管理员。不同的用户拥有不同的权限,各自完成各自的管理功能,不同的用户看到不同的系统功能。用MySql创建后台数据库,然后利用JavaBeans编写程序实现对数据库的操作,用Struts控制业务逻辑层的跳转,为了调整系统的负载平衡用Ajax实现胖客户端来完成与数据库的异步交互,主要功能模块包括: 会员的主要功能模块包括: (1)会员管理(会员注册,会员登陆,会员资
6
- 该程序包含了完整的实体结构,实现的是一个K位xK位的布斯乘法器-The program includes a complete physical structure, to achieve a K xK-bit Booth multiplier
MirrorPicConsole
- 将图像转换为其镜像输出。可以处理mac的photo booth所照的镜像图片-transform a picture to its image in the mirror
Booth-co-so-2
- Radix Booh 2.nice to see u.i uploaded this file to download the file that i need actually
booth_mul
- 乘法器 基于改进booth编码 已验证 clk-multiplier modified booth
Multiplier16
- 本文设计了一种可以实现16位有符号/无符号二进制数乘法的乘法器。该乘法器采用了补码一位乘(Booth算法), 简化了部分积的数目, 减少了某些加法运算,从而提高了运算速度。该乘法器利用Verilog代码实现,通过Modelsim软件对相应的波形进行仿真验证,并通过QuartusII软件对源码进行编译综合。-This paper designed a 16 signed/unsigned binary number multiplicat
mult_16
- 这是自己设计的16位乘法器设计,其中用了booth编码,,4-2压缩器等,-This is a 16 multiplier design of their own design, including the booth encoding 4-2 compression, etc.,
MIPS_final-version
- 以Verilog所撰寫的Booth’s Algorithm Multiplier,可加到NiosII CPU之上,完成一道NiosII CPU的新指令。-Written by Verilog Booth,' s Algorithm Multiplier can be added to the above NiosII CPU to complete a the Nios II CPU command.
pipeline
- 以Verilog撰寫而成的Booth’s Algorithm Multiplier,並以Pipeline方式實現。-Written in the Verilog Booth' s Algorithm Multiplier, and the Pipeline way.
Digital_multiplier_code
- digital_multiplier_code in VHDL (including CSA, Booth algorithm, wallace tree)
v16bbit_boothe
- verilog程序源码,实现两个16bit数乘法,使用booth算法,一种基于状态机实现,分层层次为datapath与controller两个子模块,testBench测试通过 -verilog program source code, and two 16bit multiplication using booth algorithm, based on the state machine implementation, the