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AS_FIFO_DESIGN_Verilog
- 使用Verilog硬件描述语言完成了一个异步FIFO的设计,供相关硬件开发人员参考。-Verilog hardware descr iption language used to complete an asynchronous FIFO design, hardware development for the relevant reference.
75448172geleicounter
- 这是异步fifo的vhdl实现代码,已经在FPGA上通过实践证明,运行状态良好-This is the asynchronous fifo realize the VHDL code has been adopted in the FPGA Practice has proved that running in good condition
clk
- 通过一个主时钟信号完成异步FIFO读写时钟信号的产生。编译通过实现功能。-Through a master clock signal the completion of asynchronous FIFO read and write clock signal generation. Compiler through the implementation function.
asynFifo
- 异步fifo在IC设计中,非常重要;是异步时钟域同步方法-Asynchronous fifo in IC design, is very important are asynchronous clock domain synchronization
fifo1
- 异步FIFO的设计 包括testbench 已调试成功-Asynchronous FIFO design includes testbench debug success has been
FIFO_Design
- 一种基于格雷码的异步FIFO设计与实现,8*8位的fifo VHDL 源码-Gray-code based on the Asynchronous FIFO Design and Implementation
ASYNCFIFO
- 异步FIFO的FPGA实现,XILINX FPGA, ISE ,VHDL语言实现-asynchronous fifo
fifo_sync
- 用VHDL语言编写的FPGA程序,实现异步FIFO的功能。这个程序设计十分巧妙,精简。 -vhdl fifo sound code
fifo
- 异步fifo,用Verilog编写,包含testbench,已经通过modelsim调试,内含文档和波形图-Asynchronous fifo, to prepare to use Verilog, including testbench, debug modelsim has passed, including documents and wave
asynfifo
- 异步fifo,用Verilog编写,包含testbench,已经通过调试,需要的下载-Asynchronous fifo, to prepare to use Verilog, including testbench, debugging has been passed, the need to download
fifo
- 格雷码对地址编码的异步FIFO的实现方法-Gray code encoding to address the realization of the asynchronous FIFO method
FIFO
- 异步fifo,希望能给大家带来帮助-异步fifo
Asynchronous_FIFO_v6_1
- 详细介绍了异步FIFO的设计方法,以及fpga的仿真波形-Described in detail the design of asynchronous FIFO method and the simulation waveform fpga
VHDLbasicExampleDEVELOPEMENTsoursE
- 这里收录的是《VHDL基础及经典实例开发》一书中12个大型实例的源程序。为方便读者使用,介绍如下: Chapter3:schematic和vhdl文件夹,分别是数字钟设计的原理图文件和VHDL程序; Chapter4:multiplier文件夹,串并乘法器设计程序(提示:先编译程序包); Chapter5:sci文件夹,串行通信接口设计程序; Chapter6:watchdog文件夹,看门狗设计程序; Chapter
fifo_design
- 异步fifo的设计,能够很好的的完成,数据的缓冲,内部有ram存储器-The design of asynchronous fifo, Asynchronous fifo design, can be a good completion of the data buffer, internal ram memory
async_fifo
- 异步fifo 源程序代码 欢迎大家学习 用VHDL语言编写-asy fifo
afifo_0916
- 异步FIFO,使用XILINX产品实现,可以通过改参数来重新修改深度和位宽-Asynchronous FIFO, using the XILINX product realization, you can change parameters to re-modify the depth and Width
Verilog
- 异步fifo的经典写法,使用verilog语言编写的。-Asynchronous fifo' s classic formulation, using verilog language.
asfifodesign
- 异步fifo设计文档,里面包括详细的verilog设计方案及代码。fifo设计是通信中必然设计的设计-a fifo design with code inside, using verilog language
ASY_FIFO
- 异步FIFO的设计,对整个异步FIFO的过程进行了详细的介绍-the design of the asy FIFO