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[VHDL编程] lab1_multicycle_dds
说明:生成一个多周期直接信号数字合成器的Verilog代码,已在matlab中测试生成信号的频谱纯度符号要求-Generate more than one cycle of the signal direct digital synthesizer Verilog code, has been tested symbol require spectral purity of the signal generated in matlab<林森> 在 2025-09-14 上传 | 大小:3.18mb | 下载:0
[软件工程] lab2.tar
说明:32 bit alu using structural verilog. has test benches t-32 bit alu using structural verilog. has test benches too<gameproring> 在 2025-09-14 上传 | 大小:10kb | 下载:0
[系统编程] helloprogramhere
说明:visualization this is very much important<saathisudip> 在 2025-09-14 上传 | 大小:1kb | 下载:0
[matlab例程] voice-signal-processing
说明:用matlab读取一个语音信号,对其进行变调,回音灯各种处理的设计报告,含代码与仿真图-Reads a speech signal with matlab, its tone, design reports echo lamp various treatments, including code and simulation map<林森> 在 2025-09-14 上传 | 大小:270kb | 下载:0
[ListView/ListBox] SampleProject
说明:Just A Sample Doc To Start With<lino> 在 2025-09-14 上传 | 大小:19.57mb | 下载:0
[VHDL编程] start_lab4
说明:用Verilog设计一个时间基准电路和带使能的多周期计数器,并在此基础是设计一个简单的秒表0.0-10.0计数- Verilog design with a time reference circuit and with enable multi-cycle counter, and on this basis is to design a simple stopwatch count 0.0-10.0<林森> 在 2025-09-14 上传 | 大小:21.16mb | 下载:0