[VHDL编程] EnergyEfficientVLSIArchitectureforLinearTurboEqua

说明：Energy efficient for turbo encoder decoder
<suresh> 在 2025-06-12 上传 | 大小：524kb | 下载：0

[VHDL编程] IterativeDecodingofBinary

说明：In this paper, energy efficient VLSI architectures for linear turbo equalization are studied. Linear turbo equalizers exhibit dramatic bit error rate (BER) improvement over conventional equalizers by enabling a form of joint equalization and deco
<suresh> 在 2025-06-12 上传 | 大小：1.45mb | 下载：0

[VHDL编程] MapAlgorithm

说明：However, turbo equalizers can be computationally complex and hence require significant power consumption. In this paper, we present an energy-efficient VLSI architecture for such linear turbo equalizers. Key architectural techniques include elimi
<suresh> 在 2025-06-12 上传 | 大小：1.25mb | 下载：0

[VHDL编程] RECURSIVEALGORITHMFOREFFICIENTMAPDECODING

说明：Early termination enables powering down parts of the soft-input soft-output (SISO) equalizer and decoder thereby saving power.
<suresh> 在 2025-06-12 上传 | 大小：102kb | 下载：0

[VHDL编程] VerilogLangRefManual

说明：Simulation results show that energy savings in the range 30–60 and 10–60 are achieved in equalization and decoding, respectively. Furthermore, we present finite precision requirements of the linear turbo equalizer and an efficient rescaling metho
<suresh> 在 2025-06-12 上传 | 大小：1.22mb | 下载：0

[VHDL编程] CPU

说明：CPU的构造，采用veril语言 对计算机专业同学有用-CPU
<姚琪儿> 在 2025-06-12 上传 | 大小：2.46mb | 下载：0

[VHDL编程] polyphase

说明：The current portion of the collaboration has involved the feasibilty and implementation of a Polyphase Filter bank using various FPGAs and hardware architectures
<vadik> 在 2025-06-12 上传 | 大小：267kb | 下载：0

[VHDL编程] AD6635

说明：The AD6635 is a multimode, 8-channel, digital Receive Signal Processor (RSP) capable of processing up to four WCDMA channels
<vadik> 在 2025-06-12 上传 | 大小：497kb | 下载：0

[VHDL编程] ip_digifrec

说明：The Digital IF Receiver megafunction combines a quadrature NCO and a digital mixer to translate the input IF signal down to baseband
<vadik> 在 2025-06-12 上传 | 大小：67kb | 下载：0

[VHDL编程] prog_dds

说明：FPGA VHDL DDS程序，采用FPGA实现1hz到100khz可调的dds程序，频率调节步长是变化的。-FPGA VHDL DDS program, using FPGA to achieve 1hz to 100khz adjustable dds procedures, the frequency adjustment step size is changing.
<张鹏> 在 2025-06-12 上传 | 大小：1.18mb | 下载：0

[VHDL编程] s

说明：基于VHDL的选择运算器，可以通过选择端选择加减与或四种运算，每个时钟周期刷新结果一次。注释已给出。-The choice of VHDL-based computing device, you can choose by selecting the side addition and subtraction with or four kinds of operations, the results of one per clock cycle refresh. Note has been gi
<cckaa> 在 2025-06-12 上传 | 大小：1kb | 下载：0

[VHDL编程] seven

说明：基于VHDL实现输入控制7段数码管的代码，分别用逻辑表达式法和真值表法实现。-VHDL-based implementation of digital control input control 7-segment code, respectively, a logical expression method and truth table method to achieve.
<cckaa> 在 2025-06-12 上传 | 大小：1kb | 下载：0