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[VHDL编程] hw3
说明：Write VHDL codes to model an 8-bit counter that counts every second. It counts from your last two digits of your student ID to your next two digits of your student ID. If the last two digits are greater than the next two digits, the counters counts d<vinay> 在 2025-06-11 上传 | 大小：344kb | 下载：0
[VHDL编程] hw5
说明：Design a 2-digit stopwatch that ticks every second. A switch is used to start and stop the time. When the switch is pushed, the time will start and when it is pushed again, the time will stop. In order for the switch to work properly, the switch must<vinay> 在 2025-06-11 上传 | 大小：1.31mb | 下载：0
[VHDL编程] hw4
说明：Write VHDL codes to show, on two 7-segment LEDs, the binary coded decimal (BCD) equivalence of the binary representation of the state of eight switches. Use a function to perform the specified task. Assume that the 7-segment LEDs are turned on with l<vinay> 在 2025-06-11 上传 | 大小：324kb | 下载：0
[VHDL编程] reg-a-wire
说明：verilog 使用中reg 与 wire 区别及使用方法-verilog using the difference between reg and wire and method of use<张树强> 在 2025-06-11 上传 | 大小：2kb | 下载：0
[VHDL编程] ad706_7276
说明：DA7276 的verilog 代码，时序还算精准，可直接复制使用-DA7276 of the verilog code, timing still accurate, can be directly copied using<huangying> 在 2025-06-11 上传 | 大小：42kb | 下载：0
[VHDL编程] ledwatertest
说明：一个用verilog 编写的流水灯程序，对于初学者比较有用，主要用于理解状态机转换。-Written in a flowing light with verilog program more useful for beginners, mainly for the understanding of the state machine transition.<huangying> 在 2025-06-11 上传 | 大小：35kb | 下载：0
[VHDL编程] carry-ripple
说明：carry ripple adder code (whole project) in vhdl using xilinx tool. VHD file has source code<aaqib> 在 2025-06-11 上传 | 大小：296kb | 下载：0