资源列表
[VHDL编程] 90477673uart(Verilog)
说明:uart通讯程序源代码,采用verilog编写-urat program(verilog)<te> 在 2025-06-10 上传 | 大小:11kb | 下载:0
[VHDL编程] n_evendivider
说明:很好的分频代码,能够实现奇数或偶数的分频。-A very good division.it can realize the division of odd and even numbers.<mxf> 在 2025-06-10 上传 | 大小:208kb | 下载:0
[VHDL编程] module-horse
说明:跑马灯代码能够让你的LED灯按照你的思路闪烁,基于这种原理可以设计很漂亮的装饰灯。-the horse light can make your led light lits as you thought,it can also design some wonderful lights for decoration based on this priciple.<mxf> 在 2025-06-10 上传 | 大小:3kb | 下载:0
[VHDL编程] timescale-1ns
说明:这是一款由晶振产生的脉冲控制的数字钟,可以从00:00:00到23:59:59之间进行计时。-this is a clolk controlled by continuious pulse.it can timing from 00:00:00 to 23:59:59.<mxf> 在 2025-06-10 上传 | 大小:8kb | 下载:0
[VHDL编程] 1.-[Ebook]-Digital-Design-Principles-and-Wakerly-
说明:a good book about digital<ngocphukmt> 在 2025-06-10 上传 | 大小:4.87mb | 下载:0
[VHDL编程] SPI_slave-fpga_arm
说明:使用SPI接口,使得FPGA与ARM进行通讯. 设置寄存器和读取数据-communicateion FPGA and ARM using SPI<何有> 在 2025-06-10 上传 | 大小:80kb | 下载:0
[VHDL编程] alu
说明:This 8 bit unsigned arithematic logical unit(ALU). This code is developed in VHDL language and compatible with any VHDL softeware like xilinx,quartus. This ALU performs addition,subtraction,multiplication,and,or,and not and pass input functions.-<chunduru> 在 2025-06-10 上传 | 大小:92kb | 下载:0
[VHDL编程] Serpar
说明:A serial to parallel converter is somewhat the reverse of the operation of parallel to serial converter. The data comes serially from the input port SERIN. The parallel data is output from DOUT port. Output port DRDY is asserted ‘1’ when the start bi<riadh> 在 2025-06-10 上传 | 大小:1kb | 下载:0
[VHDL编程] QPSKmapping
说明:CODE OF QPSK:The mapping module used is QPSK type of modulation<riadh> 在 2025-06-10 上传 | 大小:1kb | 下载:0