[VHDL编程] ps2interface

说明：this a fpga sparttan 3e based project in which i have made a game based on vga interface . this file is the supporting file for ps/2 interface .-this is a fpga sparttan 3e based project in which i have made a game based on vga interface . t
<yasir > 在 2025-06-22 上传 | 大小：5kb | 下载：0

[VHDL编程] game

说明：this a fpga sparttan 3e based project in which i have made a game based on vga interface . this file is the main file included in the project.-this is a fpga sparttan 3e based project in which i have made a game based on vga interface . thi
<yasir > 在 2025-06-22 上传 | 大小：2kb | 下载：0

[VHDL编程] keyb

说明：this a fpga sparttan 3e based project in which i have made a game based on vga interface . this file is the supporting file for keyboard interface and it also included a intro.vhdl file required for the startup animation file.-this is a fpga spa
<yasir > 在 2025-06-22 上传 | 大小：2kb | 下载：0

[VHDL编程] jianpanjuzhen

说明：8*8键盘矩阵 用作单片机 8*8键盘矩阵 用作单片机 8*8键盘矩阵 用作单片机-8* 8 keyboard matrix used as a microcontroller 8* 8 keyboard matrix used as a microcontroller 8* 8 keyboard matrix used as a microcontroller 8* 8 keyboard matrix used as a MCU
<翟召健> 在 2025-06-22 上传 | 大小：39kb | 下载：0

[VHDL编程] FIR

说明：FIR filter up to 128x
<mlapov> 在 2025-06-22 上传 | 大小：23.44mb | 下载：0

[VHDL编程] Processor_alu

说明：this Code is in verilog HDL. This Code is for piplined processor with 4 opcode. this will work in three cycle latch, decode and exicute.. test bench for xilinx ise is laos given
<Yogesh PAtel> 在 2025-06-22 上传 | 大小：4kb | 下载：0

[VHDL编程] countor

说明：This code for countor . it is design in verilog HDL.
<Yogesh PAtel> 在 2025-06-22 上传 | 大小：1kb | 下载：0

[VHDL编程] hello_world

说明：欢迎大家使用该程序，是在FPGA下使用开发的。请大家使用。-Welcome to use the program is to use FPGA development. Please use the.
<刘金才> 在 2025-06-22 上传 | 大小：2kb | 下载：0

[VHDL编程] 8051_source_2.8a

说明：8051内核的hdl代码，实际上是verilog格式不过上载页面只有一个vhdl选择，值得一读， 里面对仿真和验证的说明很有含金量-the hdl code of 8051 core
<mars> 在 2025-06-22 上传 | 大小：38kb | 下载：0

[VHDL编程] VHDLtransmitter

说明：这是我做UART时候做的一个发送器的源码，希望对大家有用。-This is what I did do a UART transmitter when the source and hope for all of us.
<邹正> 在 2025-06-22 上传 | 大小：3kb | 下载：0

[VHDL编程] DE2_NIOS_Lite_11.tar

说明：DE2-70,NIOS reference file,
<huang> 在 2025-06-22 上传 | 大小：972kb | 下载：0

[VHDL编程] adder

说明：vhdl adder with two input 4-bit and output of 4 bits and carry
<querias> 在 2025-06-22 上传 | 大小：1kb | 下载：0