资源列表
[VHDL编程] Writing-Testbenches-using-System-Verilog.tar
说明：Writing Testbenches Using SystemVerilog offers a clear blueprint of a verification process that aims for first-time success using the SystemVerilog language. From simulators to source management tools, from specification to functional coverage, from<ynona> 在 2025-06-10 上传 | 大小：2.65mb | 下载：0
[VHDL编程] sdram_yadmc.tar
说明：/* * Yet Another Dynamic Memory Controller * Copyright (C) 2008 Sebastien Bourdeauducq - http://lekernel.net * This file is part of Milkymist. * * Milkymist is free software you can redistribute it and/or modify it * under the terms<shangdawei> 在 2025-06-10 上传 | 大小：21kb | 下载：0
[VHDL编程] sdram_vhd_134
说明：Design Descr iption: The SDRAM controller is designed for a Virtex device. It s simulated with Micron SDRAM models. The design is verified with backannotated simulation at 125MHz. For a full functional descr iption see Application Note 134: h<shangdawei> 在 2025-06-10 上传 | 大小：398kb | 下载：0
[VHDL编程] Micron_SDRAM_CNTR
说明：/****************************************************************************** * * File Name: sdrm.v * Version: 1.14 * Date: Sept 9, 1999 * Descr iption: Top level module * Dependencies: sdrm_t, sys_int * * Company: Xilinx * *<shangdawei> 在 2025-06-10 上传 | 大小：291kb | 下载：0
[VHDL编程] Operating_Systems
说明：The folder includes various algorithms of Operating Systems such as Bankers algorithm,C-Scan,FIFO,Shortest job first,Round Robin etc. All are implemented in C.<shaikh sajid ikbal> 在 2025-06-10 上传 | 大小：8kb | 下载：0
[VHDL编程] nLint_Quick-Start
说明：nLint入门教程 包括如何设置nLint的规则 等各种-nLint Introduction<fastwind> 在 2025-06-10 上传 | 大小：1.32mb | 下载：0
[VHDL编程] The-Specification-of-SDC
说明：综合约束文件SDC的写法说明 synopsys 出品-Using the Synopsys Design Constraints Format Application Note<fastwind> 在 2025-06-10 上传 | 大小：115kb | 下载：0
[VHDL编程] The-verilog-introduction-of-Huawei
说明：华为的verilog入门教程。总的来说跟一般教程没太大区别，比较简单简洁。-Introduction of verilog in Huawei<fastwind> 在 2025-06-10 上传 | 大小：257kb | 下载：0