[VHDL编程] VHDL-lab4

说明：VHDL stands for Very High speed IC Hardware descr iption language.
<Madan Neupane> 在 2025-06-17 上传 | 大小：348kb | 下载：0

[VHDL编程] bpsk

说明：BPSK- Design and implementation of BSPK modulation and demodulation.. using sine wave-BPSK- Design and implementation of BSPK modulation and demodulation.. using sine wave..
<kalyan> 在 2025-06-17 上传 | 大小：297kb | 下载：0

[VHDL编程] dmf_vhdl

说明：digital Matched Filter design - including the clock synchronization of the design and its implementation-digital Matched Filter design - including the clock synchronization of the design and its implementation..
<kalyan> 在 2025-06-17 上传 | 大小：413kb | 下载：0

[VHDL编程] dptaal

说明：Design of Adiabatic logic using VHDL
<kalyan> 在 2025-06-17 上传 | 大小：347kb | 下载：0

[VHDL编程] COMB

说明：We use port map statement to achieve the structural model (components instantiations). The following example shows how to write the program to incorporate multiple components in the design of a more complex circuit. In order to simulate the design, a
<sam> 在 2025-06-17 上传 | 大小：1kb | 下载：0

[VHDL编程] CALIBRATION

说明：Calibration is a comparison between measurements – one of known magnitude or correctness made or set with one device and another measurement made in as similar a way as possible with a second device. The device with the known or assigned correctness
<GOPALAKRISHNAN E> 在 2025-06-17 上传 | 大小：1kb | 下载：0

[VHDL编程] all-code-files

说明：code for virus detection processor in vhdl
<kusumanchi> 在 2025-06-17 上传 | 大小：17kb | 下载：0

[VHDL编程] finalcode

说明：vhdl code for simple virus detection processor. it can also develop in verilog
<kusumanchi> 在 2025-06-17 上传 | 大小：14kb | 下载：0

[VHDL编程] d-Flip-Flop

说明：D flip flop and some other codes added together recomended use is adding layer not use in a single bench
<Dou> 在 2025-06-17 上传 | 大小：2kb | 下载：0

[VHDL编程] mux8to1_with_if

说明：this code to input 8 different data and make them out sequentialy -this code to input 8 different data and make them out sequentialy
<freaker> 在 2025-06-17 上传 | 大小：18kb | 下载：0

[VHDL编程] Projects

说明：this is sub and adder in vhdl &writed in ISE
<mohammad> 在 2025-06-17 上传 | 大小：1kb | 下载：0

[VHDL编程] verilog-mode

说明：verilog mode for gvim
<tguy99999> 在 2025-06-17 上传 | 大小：91kb | 下载：0