[VHDL编程] test_rtls

说明：RTl hardware generation
<ayaz> 在 2025-06-23 上传 | 大小：722kb | 下载：0

[VHDL编程] usb

说明：usb2.0 vhdl 控制源码 资料可信 完全自编写。-usb2.0 vhdl
<rkl110> 在 2025-06-23 上传 | 大小：1kb | 下载：0

[VHDL编程] FPGA__source-code__Verilog

说明：FPGA部分基础功能源代码，适合初学者进行学习仿真，代码可读性强，通俗易懂，逻辑清晰。包括触发器，全加器，分频，并串转换，计数器，序列发生器等Verilog语言源代码。- Part of the basic functions of the source code for FPGA.Suitable for beginners to learn the simulation, the code readable, easy to understand, clear logic. Includ
<张秋爽> 在 2025-06-23 上传 | 大小：1.82mb | 下载：0

[VHDL编程] ethcomm

说明：转：FPGA Ethernet Communications Interface.-FPGA Ethernet Communications Interface
<richard> 在 2025-06-23 上传 | 大小：366kb | 下载：0

[VHDL编程] state_machine

说明：适合初学者。简单的状态机，有8个状态,数码管输出当前状态的编号.基于Mars-XC3S400-F实验板-Suitable for beginners.A simple state machine, there are eight state, digital tube output the serial number of the current state. Based on Mars- XC3S400-f experiment board
<龙晓磊> 在 2025-06-23 上传 | 大小：1.42mb | 下载：0

[VHDL编程] seg70

说明：适合fpga，verilog初学者。按一定的频率轮流向各个数码管的COM端送出低电平，同时送出对应的数据给各段。以动态扫描方式在8位数码管“同时”显示0 7-According to certain frequency in turn to various digital tube COM client sends out the low level, at the same time to send out the corresponding data to the paragraphs.In
<龙晓磊> 在 2025-06-23 上传 | 大小：1.42mb | 下载：0

[VHDL编程] test

说明：Test Pattern files used for testing on embedded development board
<Jain> 在 2025-06-23 上传 | 大小：1kb | 下载：0

[VHDL编程] CRC

说明：能够实现S模式询问应答过程中的AP域编码模块，该模块完全按照260B协议编码-Mode S transponder can be achieved in the process of inquiry AP domain encoding module, which is fully in accordance with the 260B protocol encoding
<赵强> 在 2025-06-23 上传 | 大小：3kb | 下载：0

[VHDL编程] Pre-Emphasis

说明：A novel approach to equalization of high-speed serial links combines both amplitude pre-emphasis to correct for intersymbol interference and phase pre-emphasis to compensate for deterministic jitter, in particular, data-dependent jitter. Phase pree
<vel> 在 2025-06-23 上传 | 大小：7.26mb | 下载：0

[VHDL编程] VLSI4

说明：The mismatch drift of dynamic circuits, which must be corrected by precharging before activation, is a fundamental process and device reliability issue for very large scale integration (VLSI) circuits. In this paper, we report the consequences
<vel> 在 2025-06-23 上传 | 大小：22.63mb | 下载：0

[VHDL编程] 1

说明：than dc parameter (saturation current, threshold voltage, etc.) degradation. An electron beam probing was performed on a 64-Mb DRAM chip to detect the influence of gate capacitance variation in dynamic circuit blocks before and after hot-carr
<vel> 在 2025-06-23 上传 | 大小：19.95mb | 下载：0

[VHDL编程] 2

说明： for the first time, the impact of hotcarrier-induced gate capacitance variation on dynamic circuits in a VLSI chip. To investigate the mismatch drift due to the hot-carrier-induced gate capacitance variation, internal probing was performed at
<vel> 在 2025-06-23 上传 | 大小：12.09mb | 下载：0