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[VHDL编程] hdbn
说明:This “core” is actually two cores – an HDB3/HDB2/B3ZS Encoder that converts NRZ data into P and N pulses according to ITU-T G.703, and a HDB3/HDB2/B3ZS Decoder that converts P and N pulses into NRZ data according to ITU-T G.703. Note: HDB2 and<fronders> 在 2025-07-09 上传 | 大小:9kb | 下载:0
[VHDL编程] Interleaver_Deinterleaver
说明:通信中卷积交织/解交织FPGA源程序,采用verilogHDL代码实现,包含测试程序,经过验证。-Communication in the convolutional interleaving/de interleaving FPGA source program, using verilogHDL code to achieve, including test procedures, after verification.<ranbowang> 在 2025-07-09 上传 | 大小:9kb | 下载:0
[VHDL编程] Huffman_enc_dec
说明:Huffman encoder decoder verilog<carlos andres> 在 2025-07-09 上传 | 大小:9kb | 下载:0